Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	733786340	578728519	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	733786340	3782895	0	0
GntImpliesValid_A	733786340	3782895	0	0
GrantKnown_A	733786340	578728519	0	0
IdxKnown_A	733786340	578728519	0	0
IndexIsCorrect_A	733786340	3782895	0	0
LockArbDecision_A	733786340	0	0	0
NoReadyValidNoGrant_A	733786340	0	0	0
ReadyAndValidImplyGrant_A	733786340	3782895	0	0
ReqAndReadyImplyGrant_A	733786340	3782895	0	0
ReqImpliesValid_A	733786340	3782895	0	0
ReqStaysHighUntilGranted0_M	733786340	0	0	0
RoundRobin_A	733786340	3	0	974
ValidKnown_A	733786340	578728519	0	0
gen_data_port_assertion.DataFlow_A	733786340	3782895	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	578728519	0	0
T1	3453	3396	0	0
T2	3060	3005	0	0
T3	2034704	1148850	0	0
T4	112184	96501	0	0
T5	1501571	1028219	0	0
T6	645880	1529229	0	0
T7	165290	132417	0	0
T8	661473	578724	0	0
T9	641252	412379	0	0
T10	1011316	649648	0	0
T11	114564	57214	0	0
T12	26294	26142	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3782895	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	2034704	13473	0	0
T4	112184	832	0	0
T5	1501571	13851	0	0
T6	645880	15609	0	0
T7	165290	832	0	0
T8	661473	832	0	0
T9	641252	832	0	0
T10	1011316	9723	0	0
T11	114564	2624	0	0
T12	52588	0	0	0
T13	0	1250	0	0
T15	0	12216	0	0
T23	0	360	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T32	0	3689	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0
T43	0	4	0	0
T44	0	356	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3782895	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	2034704	13473	0	0
T4	112184	832	0	0
T5	1501571	13851	0	0
T6	645880	15609	0	0
T7	165290	832	0	0
T8	661473	832	0	0
T9	641252	832	0	0
T10	1011316	9723	0	0
T11	114564	2624	0	0
T12	52588	0	0	0
T13	0	1250	0	0
T15	0	12216	0	0
T23	0	360	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T32	0	3689	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0
T43	0	4	0	0
T44	0	356	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	578728519	0	0
T1	3453	3396	0	0
T2	3060	3005	0	0
T3	2034704	1148850	0	0
T4	112184	96501	0	0
T5	1501571	1028219	0	0
T6	645880	1529229	0	0
T7	165290	132417	0	0
T8	661473	578724	0	0
T9	641252	412379	0	0
T10	1011316	649648	0	0
T11	114564	57214	0	0
T12	26294	26142	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	578728519	0	0
T1	3453	3396	0	0
T2	3060	3005	0	0
T3	2034704	1148850	0	0
T4	112184	96501	0	0
T5	1501571	1028219	0	0
T6	645880	1529229	0	0
T7	165290	132417	0	0
T8	661473	578724	0	0
T9	641252	412379	0	0
T10	1011316	649648	0	0
T11	114564	57214	0	0
T12	26294	26142	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3782895	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	2034704	13473	0	0
T4	112184	832	0	0
T5	1501571	13851	0	0
T6	645880	15609	0	0
T7	165290	832	0	0
T8	661473	832	0	0
T9	641252	832	0	0
T10	1011316	9723	0	0
T11	114564	2624	0	0
T12	52588	0	0	0
T13	0	1250	0	0
T15	0	12216	0	0
T23	0	360	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T32	0	3689	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0
T43	0	4	0	0
T44	0	356	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3782895	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	2034704	13473	0	0
T4	112184	832	0	0
T5	1501571	13851	0	0
T6	645880	15609	0	0
T7	165290	832	0	0
T8	661473	832	0	0
T9	641252	832	0	0
T10	1011316	9723	0	0
T11	114564	2624	0	0
T12	52588	0	0	0
T13	0	1250	0	0
T15	0	12216	0	0
T23	0	360	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T32	0	3689	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0
T43	0	4	0	0
T44	0	356	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3782895	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	2034704	13473	0	0
T4	112184	832	0	0
T5	1501571	13851	0	0
T6	645880	15609	0	0
T7	165290	832	0	0
T8	661473	832	0	0
T9	641252	832	0	0
T10	1011316	9723	0	0
T11	114564	2624	0	0
T12	52588	0	0	0
T13	0	1250	0	0
T15	0	12216	0	0
T23	0	360	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T32	0	3689	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0
T43	0	4	0	0
T44	0	356	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3782895	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	2034704	13473	0	0
T4	112184	832	0	0
T5	1501571	13851	0	0
T6	645880	15609	0	0
T7	165290	832	0	0
T8	661473	832	0	0
T9	641252	832	0	0
T10	1011316	9723	0	0
T11	114564	2624	0	0
T12	52588	0	0	0
T13	0	1250	0	0
T15	0	12216	0	0
T23	0	360	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T32	0	3689	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0
T43	0	4	0	0
T44	0	356	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3	0	974
T45	233903	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	1482	0	0	1
T49	790267	0	0	1
T50	2166	0	0	1
T51	16300	0	0	1
T52	693810	0	0	1
T53	122672	0	0	1
T54	110657	0	0	1
T55	238291	0	0	1
T56	1703	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	578728519	0	0
T1	3453	3396	0	0
T2	3060	3005	0	0
T3	2034704	1148850	0	0
T4	112184	96501	0	0
T5	1501571	1028219	0	0
T6	645880	1529229	0	0
T7	165290	132417	0	0
T8	661473	578724	0	0
T9	641252	412379	0	0
T10	1011316	649648	0	0
T11	114564	57214	0	0
T12	26294	26142	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733786340	3782895	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	2034704	13473	0	0
T4	112184	832	0	0
T5	1501571	13851	0	0
T6	645880	15609	0	0
T7	165290	832	0	0
T8	661473	832	0	0
T9	641252	832	0	0
T10	1011316	9723	0	0
T11	114564	2624	0	0
T12	52588	0	0	0
T13	0	1250	0	0
T15	0	12216	0	0
T23	0	360	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T32	0	3689	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0
T43	0	4	0	0
T44	0	356	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153656068	27206521	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	153656068	583925	0	0
GntImpliesValid_A	153656068	583925	0	0
GrantKnown_A	153656068	27206521	0	0
IdxKnown_A	153656068	27206521	0	0
IndexIsCorrect_A	153656068	583925	0	0
LockArbDecision_A	153656068	0	0	0
NoReadyValidNoGrant_A	153656068	0	0	0
ReadyAndValidImplyGrant_A	153656068	583925	0	0
ReqAndReadyImplyGrant_A	153656068	583925	0	0
ReqImpliesValid_A	153656068	583925	0	0
ReqStaysHighUntilGranted0_M	153656068	0	0	0
RoundRobin_A	153656068	0	0	0
ValidKnown_A	153656068	27206521	0	0
gen_data_port_assertion.DataFlow_A	153656068	583925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	27206521	0	0
T2	360	360	0	0
T3	881094	34992	0	0
T4	15588	0	0	0
T5	469009	50032	0	0
T6	111028	304600	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	583925	0	0
T3	881094	1257	0	0
T4	15588	0	0	0
T5	469009	1211	0	0
T6	111028	4065	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T13	0	1250	0	0
T15	0	6373	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	583925	0	0
T3	881094	1257	0	0
T4	15588	0	0	0
T5	469009	1211	0	0
T6	111028	4065	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T13	0	1250	0	0
T15	0	6373	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	27206521	0	0
T2	360	360	0	0
T3	881094	34992	0	0
T4	15588	0	0	0
T5	469009	50032	0	0
T6	111028	304600	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	27206521	0	0
T2	360	360	0	0
T3	881094	34992	0	0
T4	15588	0	0	0
T5	469009	50032	0	0
T6	111028	304600	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	583925	0	0
T3	881094	1257	0	0
T4	15588	0	0	0
T5	469009	1211	0	0
T6	111028	4065	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T13	0	1250	0	0
T15	0	6373	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	583925	0	0
T3	881094	1257	0	0
T4	15588	0	0	0
T5	469009	1211	0	0
T6	111028	4065	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T13	0	1250	0	0
T15	0	6373	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	583925	0	0
T3	881094	1257	0	0
T4	15588	0	0	0
T5	469009	1211	0	0
T6	111028	4065	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T13	0	1250	0	0
T15	0	6373	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	583925	0	0
T3	881094	1257	0	0
T4	15588	0	0	0
T5	469009	1211	0	0
T6	111028	4065	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T13	0	1250	0	0
T15	0	6373	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	27206521	0	0
T2	360	360	0	0
T3	881094	34992	0	0
T4	15588	0	0	0
T5	469009	50032	0	0
T6	111028	304600	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T13	0	33896	0	0
T15	0	142872	0	0
T24	0	288	0	0
T25	0	205360	0	0
T26	0	86904	0	0
T27	0	25112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	583925	0	0
T3	881094	1257	0	0
T4	15588	0	0	0
T5	469009	1211	0	0
T6	111028	4065	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	0	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T13	0	1250	0	0
T15	0	6373	0	0
T25	0	5374	0	0
T26	0	2931	0	0
T40	0	160	0	0
T41	0	203	0	0
T42	0	130	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153656068	125134639	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	153656068	870704	0	0
GntImpliesValid_A	153656068	870704	0	0
GrantKnown_A	153656068	125134639	0	0
IdxKnown_A	153656068	125134639	0	0
IndexIsCorrect_A	153656068	870704	0	0
LockArbDecision_A	153656068	0	0	0
NoReadyValidNoGrant_A	153656068	0	0	0
ReadyAndValidImplyGrant_A	153656068	870704	0	0
ReqAndReadyImplyGrant_A	153656068	870704	0	0
ReqImpliesValid_A	153656068	870704	0	0
ReqStaysHighUntilGranted0_M	153656068	0	0	0
RoundRobin_A	153656068	0	0	0
ValidKnown_A	153656068	125134639	0	0
gen_data_port_assertion.DataFlow_A	153656068	870704	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	125134639	0	0
T3	881094	841351	0	0
T4	15588	15588	0	0
T5	469009	414871	0	0
T6	111028	800895	0	0
T7	32524	32228	0	0
T8	82443	82228	0	0
T9	228660	228456	0	0
T10	360376	359093	0	0
T11	57282	57214	0	0
T12	26294	26142	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	870704	0	0
T3	881094	641	0	0
T4	15588	0	0	0
T5	469009	332	0	0
T6	111028	1267	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	5355	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T15	0	5843	0	0
T16	0	7644	0	0
T23	0	360	0	0
T32	0	3689	0	0
T43	0	4	0	0
T44	0	356	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	870704	0	0
T3	881094	641	0	0
T4	15588	0	0	0
T5	469009	332	0	0
T6	111028	1267	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	5355	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T15	0	5843	0	0
T16	0	7644	0	0
T23	0	360	0	0
T32	0	3689	0	0
T43	0	4	0	0
T44	0	356	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	125134639	0	0
T3	881094	841351	0	0
T4	15588	15588	0	0
T5	469009	414871	0	0
T6	111028	800895	0	0
T7	32524	32228	0	0
T8	82443	82228	0	0
T9	228660	228456	0	0
T10	360376	359093	0	0
T11	57282	57214	0	0
T12	26294	26142	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	125134639	0	0
T3	881094	841351	0	0
T4	15588	15588	0	0
T5	469009	414871	0	0
T6	111028	800895	0	0
T7	32524	32228	0	0
T8	82443	82228	0	0
T9	228660	228456	0	0
T10	360376	359093	0	0
T11	57282	57214	0	0
T12	26294	26142	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	870704	0	0
T3	881094	641	0	0
T4	15588	0	0	0
T5	469009	332	0	0
T6	111028	1267	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	5355	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T15	0	5843	0	0
T16	0	7644	0	0
T23	0	360	0	0
T32	0	3689	0	0
T43	0	4	0	0
T44	0	356	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	870704	0	0
T3	881094	641	0	0
T4	15588	0	0	0
T5	469009	332	0	0
T6	111028	1267	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	5355	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T15	0	5843	0	0
T16	0	7644	0	0
T23	0	360	0	0
T32	0	3689	0	0
T43	0	4	0	0
T44	0	356	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	870704	0	0
T3	881094	641	0	0
T4	15588	0	0	0
T5	469009	332	0	0
T6	111028	1267	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	5355	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T15	0	5843	0	0
T16	0	7644	0	0
T23	0	360	0	0
T32	0	3689	0	0
T43	0	4	0	0
T44	0	356	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	870704	0	0
T3	881094	641	0	0
T4	15588	0	0	0
T5	469009	332	0	0
T6	111028	1267	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	5355	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T15	0	5843	0	0
T16	0	7644	0	0
T23	0	360	0	0
T32	0	3689	0	0
T43	0	4	0	0
T44	0	356	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	125134639	0	0
T3	881094	841351	0	0
T4	15588	15588	0	0
T5	469009	414871	0	0
T6	111028	800895	0	0
T7	32524	32228	0	0
T8	82443	82228	0	0
T9	228660	228456	0	0
T10	360376	359093	0	0
T11	57282	57214	0	0
T12	26294	26142	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153656068	870704	0	0
T3	881094	641	0	0
T4	15588	0	0	0
T5	469009	332	0	0
T6	111028	1267	0	0
T7	32524	0	0	0
T8	82443	0	0	0
T9	228660	0	0	0
T10	360376	5355	0	0
T11	57282	0	0	0
T12	26294	0	0	0
T15	0	5843	0	0
T16	0	7644	0	0
T23	0	360	0	0
T32	0	3689	0	0
T43	0	4	0	0
T44	0	356	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426474204	426387359	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	426474204	2328266	0	0
GntImpliesValid_A	426474204	2328266	0	0
GrantKnown_A	426474204	426387359	0	0
IdxKnown_A	426474204	426387359	0	0
IndexIsCorrect_A	426474204	2328266	0	0
LockArbDecision_A	426474204	0	0	0
NoReadyValidNoGrant_A	426474204	0	0	0
ReadyAndValidImplyGrant_A	426474204	2328266	0	0
ReqAndReadyImplyGrant_A	426474204	2328266	0	0
ReqImpliesValid_A	426474204	2328266	0	0
ReqStaysHighUntilGranted0_M	426474204	0	0	0
RoundRobin_A	426474204	3	0	974
ValidKnown_A	426474204	426387359	0	0
gen_data_port_assertion.DataFlow_A	426474204	2328266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	426387359	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	2328266	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	272516	11575	0	0
T4	81008	832	0	0
T5	563553	12308	0	0
T6	423824	10277	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	4368	0	0
T11	0	2624	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	2328266	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	272516	11575	0	0
T4	81008	832	0	0
T5	563553	12308	0	0
T6	423824	10277	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	4368	0	0
T11	0	2624	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	426387359	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	426387359	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	2328266	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	272516	11575	0	0
T4	81008	832	0	0
T5	563553	12308	0	0
T6	423824	10277	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	4368	0	0
T11	0	2624	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	2328266	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	272516	11575	0	0
T4	81008	832	0	0
T5	563553	12308	0	0
T6	423824	10277	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	4368	0	0
T11	0	2624	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	2328266	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	272516	11575	0	0
T4	81008	832	0	0
T5	563553	12308	0	0
T6	423824	10277	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	4368	0	0
T11	0	2624	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	2328266	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	272516	11575	0	0
T4	81008	832	0	0
T5	563553	12308	0	0
T6	423824	10277	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	4368	0	0
T11	0	2624	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	3	0	974
T45	233903	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	1482	0	0	1
T49	790267	0	0	1
T50	2166	0	0	1
T51	16300	0	0	1
T52	693810	0	0	1
T53	122672	0	0	1
T54	110657	0	0	1
T55	238291	0	0	1
T56	1703	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	426387359	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426474204	2328266	0	0
T1	3453	200	0	0
T2	2700	0	0	0
T3	272516	11575	0	0
T4	81008	832	0	0
T5	563553	12308	0	0
T6	423824	10277	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	4368	0	0
T11	0	2624	0	0