Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	428630466	3189	0	0
addr_swap_data_rd_A	428630466	652	0	0
addr_swap_mask_rd_A	428630466	582	0	0
cfg_rd_A	428630466	884	0	0
cmd_filter_0_rd_A	428630466	7022	0	0
cmd_filter_1_rd_A	428630466	7112	0	0
cmd_filter_2_rd_A	428630466	6463	0	0
cmd_filter_3_rd_A	428630466	6689	0	0
cmd_filter_4_rd_A	428630466	6737	0	0
cmd_filter_5_rd_A	428630466	6849	0	0
cmd_filter_6_rd_A	428630466	6507	0	0
cmd_filter_7_rd_A	428630466	6513	0	0
cmd_info_0_rd_A	428630466	3088	0	0
cmd_info_10_rd_A	428630466	2823	0	0
cmd_info_11_rd_A	428630466	2725	0	0
cmd_info_12_rd_A	428630466	3559	0	0
cmd_info_13_rd_A	428630466	2869	0	0
cmd_info_14_rd_A	428630466	2560	0	0
cmd_info_15_rd_A	428630466	3073	0	0
cmd_info_16_rd_A	428630466	2823	0	0
cmd_info_17_rd_A	428630466	3164	0	0
cmd_info_18_rd_A	428630466	3004	0	0
cmd_info_19_rd_A	428630466	2669	0	0
cmd_info_1_rd_A	428630466	2977	0	0
cmd_info_20_rd_A	428630466	3011	0	0
cmd_info_21_rd_A	428630466	3786	0	0
cmd_info_22_rd_A	428630466	3020	0	0
cmd_info_23_rd_A	428630466	2910	0	0
cmd_info_2_rd_A	428630466	3225	0	0
cmd_info_3_rd_A	428630466	2964	0	0
cmd_info_4_rd_A	428630466	2862	0	0
cmd_info_5_rd_A	428630466	3247	0	0
cmd_info_6_rd_A	428630466	3136	0	0
cmd_info_7_rd_A	428630466	3070	0	0
cmd_info_8_rd_A	428630466	3091	0	0
cmd_info_9_rd_A	428630466	2997	0	0
cmd_info_en4b_rd_A	428630466	833	0	0
cmd_info_ex4b_rd_A	428630466	759	0	0
cmd_info_wrdi_rd_A	428630466	855	0	0
cmd_info_wren_rd_A	428630466	885	0	0
intercept_en_rd_A	428630466	1114	0	0
intr_enable_rd_A	428630466	2840	0	0
jedec_cc_rd_A	428630466	821	0	0
jedec_id_rd_A	428630466	941	0	0
mailbox_addr_rd_A	428630466	610	0	0
payload_swap_data_rd_A	428630466	597	0	0
payload_swap_mask_rd_A	428630466	635	0	0
read_threshold_rd_A	428630466	738	0	0
tpm_access_0_rd_A	428630466	1112	0	0
tpm_access_1_rd_A	428630466	567	0	0
tpm_cfg_rd_A	428630466	1519	0	0
tpm_did_vid_rd_A	428630466	824	0	0
tpm_int_enable_rd_A	428630466	647	0	0
tpm_int_status_rd_A	428630466	629	0	0
tpm_int_vector_rd_A	428630466	574	0	0
tpm_intf_capability_rd_A	428630466	608	0	0
tpm_rid_rd_A	428630466	521	0	0
tpm_sts_rd_A	428630466	615	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3189	0	0
T92	5136	3	0	0
T93	10796	1	0	0
T94	15784	7	0	0
T95	5192	102	0	0
T96	92245	2	0	0
T97	28109	2	0	0
T98	10168	139	0	0
T100	9610	181	0	0
T110	90900	2	0	0
T111	5059	3	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	652	0	0
T78	4129	11	0	0
T94	15784	19	0	0
T96	92245	47	0	0
T100	9610	9	0	0
T110	90900	77	0	0
T111	5059	11	0	0
T117	10895	25	0	0
T121	9928	10	0	0
T141	6955	8	0	0
T151	14203	12	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	582	0	0
T78	4129	5	0	0
T94	15784	14	0	0
T96	92245	42	0	0
T110	90900	65	0	0
T111	5059	12	0	0
T117	10895	11	0	0
T121	9928	11	0	0
T126	6883	5	0	0
T141	6955	17	0	0
T151	14203	34	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	884	0	0
T78	4129	3	0	0
T94	15784	20	0	0
T96	92245	109	0	0
T110	90900	85	0	0
T111	5059	11	0	0
T117	10895	32	0	0
T121	9928	14	0	0
T126	6883	16	0	0
T141	6955	7	0	0
T151	14203	38	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	7022	0	0
T78	4129	5	0	0
T94	15784	264	0	0
T96	92245	1153	0	0
T110	90900	982	0	0
T111	5059	2	0	0
T117	10895	261	0	0
T121	9928	66	0	0
T126	6883	168	0	0
T141	6955	34	0	0
T151	14203	220	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	7112	0	0
T78	4129	2	0	0
T94	15784	234	0	0
T96	92245	731	0	0
T110	90900	1106	0	0
T111	5059	145	0	0
T117	10895	255	0	0
T121	9928	156	0	0
T126	6883	3	0	0
T141	6955	23	0	0
T151	14203	380	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	6463	0	0
T78	4129	7	0	0
T94	15784	117	0	0
T96	92245	1204	0	0
T110	90900	864	0	0
T111	5059	4	0	0
T117	10895	8	0	0
T121	9928	81	0	0
T126	6883	82	0	0
T141	6955	25	0	0
T151	14203	293	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	6689	0	0
T94	15784	280	0	0
T96	92245	807	0	0
T110	90900	1025	0	0
T111	5059	10	0	0
T117	10895	266	0	0
T121	9928	67	0	0
T126	6883	75	0	0
T141	6955	15	0	0
T151	14203	234	0	0
T152	6580	30	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	6737	0	0
T94	15784	19	0	0
T96	92245	973	0	0
T106	10545	4	0	0
T110	90900	1203	0	0
T111	5059	6	0	0
T117	10895	350	0	0
T121	9928	85	0	0
T126	6883	104	0	0
T141	6955	24	0	0
T151	14203	130	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	6849	0	0
T78	4129	4	0	0
T94	15784	355	0	0
T96	92245	805	0	0
T106	10545	1	0	0
T110	90900	1088	0	0
T111	5059	123	0	0
T117	10895	140	0	0
T121	9928	186	0	0
T141	6955	35	0	0
T151	14203	121	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	6507	0	0
T94	15784	140	0	0
T96	92245	994	0	0
T110	90900	1283	0	0
T111	5059	9	0	0
T117	10895	225	0	0
T121	9928	141	0	0
T126	6883	90	0	0
T141	6955	30	0	0
T151	14203	193	0	0
T152	6580	173	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	6513	0	0
T78	4129	1	0	0
T94	15784	262	0	0
T96	92245	1042	0	0
T100	9610	7	0	0
T110	90900	1346	0	0
T111	5059	122	0	0
T117	10895	141	0	0
T126	6883	7	0	0
T141	6955	3	0	0
T151	14203	118	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3088	0	0
T94	15784	93	0	0
T96	92245	282	0	0
T110	90900	594	0	0
T111	5059	18	0	0
T117	10895	59	0	0
T121	9928	37	0	0
T126	6883	4	0	0
T141	6955	20	0	0
T151	14203	80	0	0
T152	6580	18	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2823	0	0
T78	4129	4	0	0
T94	15784	82	0	0
T96	92245	394	0	0
T110	90900	461	0	0
T111	5059	6	0	0
T117	10895	131	0	0
T121	9928	18	0	0
T126	6883	12	0	0
T141	6955	1	0	0
T151	14203	101	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2725	0	0
T78	4129	7	0	0
T94	15784	78	0	0
T96	92245	372	0	0
T110	90900	393	0	0
T111	5059	13	0	0
T117	10895	6	0	0
T121	9928	31	0	0
T126	6883	35	0	0
T141	6955	4	0	0
T151	14203	72	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3559	0	0
T78	4129	11	0	0
T94	15784	71	0	0
T96	92245	465	0	0
T110	90900	385	0	0
T111	5059	10	0	0
T117	10895	187	0	0
T121	9928	66	0	0
T126	6883	10	0	0
T141	6955	8	0	0
T151	14203	60	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2869	0	0
T78	4129	9	0	0
T94	15784	23	0	0
T96	92245	413	0	0
T110	90900	476	0	0
T111	5059	48	0	0
T117	10895	117	0	0
T121	9928	22	0	0
T126	6883	64	0	0
T141	6955	38	0	0
T151	14203	56	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2560	0	0
T78	4129	4	0	0
T94	15784	20	0	0
T96	92245	387	0	0
T110	90900	363	0	0
T111	5059	14	0	0
T117	10895	111	0	0
T121	9928	93	0	0
T126	6883	37	0	0
T141	6955	6	0	0
T151	14203	19	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3073	0	0
T78	4129	10	0	0
T94	15784	116	0	0
T96	92245	450	0	0
T110	90900	508	0	0
T111	5059	2	0	0
T117	10895	94	0	0
T121	9928	54	0	0
T126	6883	19	0	0
T141	6955	9	0	0
T151	14203	51	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2823	0	0
T78	4129	12	0	0
T94	15784	28	0	0
T96	92245	321	0	0
T110	90900	411	0	0
T111	5059	51	0	0
T117	10895	51	0	0
T121	9928	82	0	0
T126	6883	52	0	0
T141	6955	22	0	0
T151	14203	59	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3164	0	0
T78	4129	3	0	0
T94	15784	136	0	0
T96	92245	453	0	0
T110	90900	404	0	0
T111	5059	47	0	0
T117	10895	101	0	0
T121	9928	21	0	0
T126	6883	9	0	0
T141	6955	9	0	0
T151	14203	70	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3004	0	0
T78	4129	6	0	0
T94	15784	130	0	0
T96	92245	382	0	0
T110	90900	381	0	0
T111	5059	7	0	0
T117	10895	14	0	0
T121	9928	61	0	0
T126	6883	43	0	0
T141	6955	1	0	0
T151	14203	66	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2669	0	0
T78	4129	17	0	0
T94	15784	66	0	0
T96	92245	307	0	0
T110	90900	377	0	0
T111	5059	3	0	0
T117	10895	66	0	0
T121	9928	61	0	0
T126	6883	22	0	0
T141	6955	4	0	0
T151	14203	106	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2977	0	0
T94	15784	19	0	0
T96	92245	443	0	0
T110	90900	453	0	0
T111	5059	8	0	0
T117	10895	138	0	0
T121	9928	30	0	0
T126	6883	33	0	0
T141	6955	29	0	0
T151	14203	83	0	0
T152	6580	55	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3011	0	0
T94	15784	81	0	0
T96	92245	519	0	0
T110	90900	444	0	0
T111	5059	39	0	0
T117	10895	115	0	0
T121	9928	23	0	0
T126	6883	9	0	0
T141	6955	15	0	0
T151	14203	40	0	0
T152	6580	61	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3786	0	0
T78	4129	6	0	0
T94	15784	155	0	0
T96	92245	454	0	0
T110	90900	560	0	0
T111	5059	46	0	0
T117	10895	114	0	0
T121	9928	70	0	0
T141	6955	24	0	0
T151	14203	53	0	0
T152	6580	5	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3020	0	0
T78	4129	6	0	0
T94	15784	124	0	0
T96	92245	320	0	0
T110	90900	315	0	0
T111	5059	71	0	0
T117	10895	131	0	0
T121	9928	111	0	0
T126	6883	35	0	0
T141	6955	37	0	0
T151	14203	53	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2910	0	0
T78	4129	7	0	0
T94	15784	161	0	0
T96	92245	485	0	0
T110	90900	482	0	0
T111	5059	58	0	0
T117	10895	6	0	0
T121	9928	79	0	0
T126	6883	54	0	0
T141	6955	10	0	0
T151	14203	38	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3225	0	0
T78	4129	11	0	0
T94	15784	145	0	0
T96	92245	352	0	0
T110	90900	451	0	0
T111	5059	9	0	0
T117	10895	124	0	0
T121	9928	32	0	0
T126	6883	9	0	0
T141	6955	31	0	0
T151	14203	56	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2964	0	0
T94	15784	18	0	0
T96	92245	403	0	0
T110	90900	527	0	0
T111	5059	6	0	0
T117	10895	93	0	0
T121	9928	30	0	0
T126	6883	43	0	0
T141	6955	6	0	0
T151	14203	130	0	0
T152	6580	67	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2862	0	0
T78	4129	8	0	0
T94	15784	172	0	0
T96	92245	353	0	0
T110	90900	480	0	0
T111	5059	4	0	0
T117	10895	43	0	0
T121	9928	31	0	0
T126	6883	16	0	0
T141	6955	16	0	0
T151	14203	52	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3247	0	0
T94	15784	32	0	0
T96	92245	421	0	0
T110	90900	451	0	0
T111	5059	18	0	0
T117	10895	165	0	0
T121	9928	29	0	0
T126	6883	35	0	0
T141	6955	18	0	0
T151	14203	45	0	0
T152	6580	42	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3136	0	0
T78	4129	9	0	0
T94	15784	73	0	0
T96	92245	513	0	0
T110	90900	460	0	0
T111	5059	53	0	0
T117	10895	16	0	0
T121	9928	26	0	0
T126	6883	28	0	0
T141	6955	39	0	0
T151	14203	68	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3070	0	0
T94	15784	172	0	0
T96	92245	436	0	0
T110	90900	293	0	0
T111	5059	42	0	0
T117	10895	9	0	0
T121	9928	25	0	0
T126	6883	34	0	0
T141	6955	22	0	0
T151	14203	79	0	0
T152	6580	70	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3091	0	0
T94	15784	57	0	0
T96	92245	276	0	0
T110	90900	419	0	0
T111	5059	56	0	0
T117	10895	100	0	0
T121	9928	51	0	0
T126	6883	1	0	0
T141	6955	23	0	0
T151	14203	10	0	0
T152	6580	2	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2997	0	0
T94	15784	65	0	0
T96	92245	528	0	0
T101	13285	6	0	0
T110	90900	462	0	0
T111	5059	57	0	0
T117	10895	48	0	0
T121	9928	79	0	0
T126	6883	20	0	0
T141	6955	52	0	0
T151	14203	104	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	833	0	0
T78	4129	11	0	0
T94	15784	34	0	0
T96	92245	79	0	0
T110	90900	107	0	0
T111	5059	9	0	0
T117	10895	17	0	0
T121	9928	14	0	0
T126	6883	11	0	0
T141	6955	37	0	0
T151	14203	17	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	759	0	0
T78	4129	6	0	0
T94	15784	21	0	0
T96	92245	62	0	0
T110	90900	118	0	0
T111	5059	20	0	0
T117	10895	3	0	0
T121	9928	1	0	0
T126	6883	22	0	0
T141	6955	1	0	0
T151	14203	43	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	855	0	0
T78	4129	5	0	0
T94	15784	17	0	0
T96	92245	96	0	0
T110	90900	88	0	0
T111	5059	8	0	0
T117	10895	20	0	0
T121	9928	9	0	0
T126	6883	7	0	0
T151	14203	30	0	0
T152	6580	6	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	885	0	0
T94	15784	34	0	0
T96	92245	64	0	0
T110	90900	128	0	0
T111	5059	16	0	0
T117	10895	16	0	0
T121	9928	5	0	0
T126	6883	2	0	0
T141	6955	26	0	0
T151	14203	30	0	0
T152	6580	4	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	1114	0	0
T78	4129	18	0	0
T94	15784	43	0	0
T96	92245	138	0	0
T110	90900	126	0	0
T111	5059	5	0	0
T117	10895	21	0	0
T121	9928	10	0	0
T126	6883	14	0	0
T141	6955	6	0	0
T151	14203	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	2840	0	0
T14	6147	53	0	0
T15	625758	0	0	0
T19	0	27	0	0
T22	0	34	0	0
T24	3326	0	0	0
T25	242466	0	0	0
T26	187643	0	0	0
T27	158867	0	0	0
T32	157413	0	0	0
T40	14332	0	0	0
T44	159585	0	0	0
T113	127189	0	0	0
T153	0	34	0	0
T154	0	30	0	0
T155	0	5	0	0
T156	0	19	0	0
T157	0	18	0	0
T158	0	35	0	0
T159	0	27	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	821	0	0
T78	4129	3	0	0
T94	15784	31	0	0
T96	92245	91	0	0
T110	90900	104	0	0
T111	5059	11	0	0
T117	10895	17	0	0
T121	9928	3	0	0
T126	6883	4	0	0
T151	14203	17	0	0
T152	6580	2	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	941	0	0
T78	4129	9	0	0
T94	15784	26	0	0
T96	92245	134	0	0
T110	90900	112	0	0
T111	5059	15	0	0
T117	10895	16	0	0
T121	9928	8	0	0
T126	6883	4	0	0
T141	6955	31	0	0
T151	14203	28	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	610	0	0
T94	15784	28	0	0
T96	92245	65	0	0
T110	90900	55	0	0
T111	5059	8	0	0
T117	10895	21	0	0
T121	9928	3	0	0
T126	6883	3	0	0
T141	6955	23	0	0
T151	14203	21	0	0
T152	6580	6	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	597	0	0
T78	4129	1	0	0
T94	15784	18	0	0
T96	92245	58	0	0
T110	90900	78	0	0
T111	5059	12	0	0
T117	10895	16	0	0
T121	9928	4	0	0
T126	6883	6	0	0
T141	6955	27	0	0
T151	14203	17	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	635	0	0
T78	4129	7	0	0
T94	15784	15	0	0
T96	92245	26	0	0
T110	90900	67	0	0
T111	5059	15	0	0
T117	10895	16	0	0
T121	9928	10	0	0
T126	6883	7	0	0
T141	6955	39	0	0
T151	14203	24	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	738	0	0
T78	4129	5	0	0
T94	15784	21	0	0
T96	92245	57	0	0
T100	9610	7	0	0
T110	90900	92	0	0
T111	5059	10	0	0
T117	10895	5	0	0
T121	9928	9	0	0
T141	6955	5	0	0
T151	14203	22	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	1112	0	0
T78	4129	6	0	0
T94	15784	24	0	0
T96	92245	191	0	0
T110	90900	161	0	0
T111	5059	8	0	0
T117	10895	26	0	0
T121	9928	29	0	0
T126	6883	15	0	0
T141	6955	16	0	0
T151	14203	39	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	567	0	0
T78	4129	5	0	0
T94	15784	12	0	0
T96	92245	45	0	0
T110	90900	58	0	0
T111	5059	4	0	0
T117	10895	12	0	0
T141	6955	32	0	0
T151	14203	27	0	0
T152	6580	6	0	0
T160	9476	2	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	1519	0	0
T78	4129	13	0	0
T94	15784	36	0	0
T96	92245	134	0	0
T110	90900	214	0	0
T111	5059	15	0	0
T117	10895	49	0	0
T121	9928	25	0	0
T126	6883	6	0	0
T141	6955	50	0	0
T151	14203	15	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	824	0	0
T78	4129	8	0	0
T94	15784	35	0	0
T96	92245	64	0	0
T110	90900	105	0	0
T111	5059	3	0	0
T117	10895	9	0	0
T121	9928	12	0	0
T126	6883	9	0	0
T141	6955	29	0	0
T151	14203	22	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	647	0	0
T78	4129	4	0	0
T94	15784	18	0	0
T96	92245	46	0	0
T110	90900	56	0	0
T111	5059	15	0	0
T117	10895	16	0	0
T121	9928	6	0	0
T126	6883	2	0	0
T141	6955	32	0	0
T151	14203	17	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	629	0	0
T78	4129	8	0	0
T94	15784	28	0	0
T96	92245	64	0	0
T110	90900	49	0	0
T111	5059	2	0	0
T117	10895	15	0	0
T121	9928	4	0	0
T126	6883	7	0	0
T141	6955	10	0	0
T151	14203	16	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	574	0	0
T78	4129	8	0	0
T94	15784	15	0	0
T96	92245	44	0	0
T106	10545	7	0	0
T110	90900	79	0	0
T111	5059	10	0	0
T117	10895	14	0	0
T121	9928	8	0	0
T141	6955	23	0	0
T151	14203	26	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	608	0	0
T94	15784	22	0	0
T96	92245	83	0	0
T110	90900	42	0	0
T111	5059	6	0	0
T117	10895	9	0	0
T121	9928	1	0	0
T126	6883	6	0	0
T141	6955	15	0	0
T151	14203	21	0	0
T152	6580	9	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	521	0	0
T78	4129	6	0	0
T94	15784	19	0	0
T96	92245	43	0	0
T110	90900	55	0	0
T111	5059	14	0	0
T117	10895	7	0	0
T121	9928	7	0	0
T126	6883	1	0	0
T141	6955	23	0	0
T151	14203	28	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	615	0	0
T78	4129	11	0	0
T94	15784	19	0	0
T96	92245	47	0	0
T110	90900	70	0	0
T111	5059	11	0	0
T117	10895	15	0	0
T126	6883	1	0	0
T141	6955	17	0	0
T151	14203	14	0	0
T152	6580	12	0	0