Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3520344	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4268974

1

T1

10987

T2

10

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4267683	1			T1	4281		T2	1		T3	1
values[0x0]	1760732	1			T1	4421		T2	7		T3	2
values[0x1]	1760903	1			T1	4374		T2	3		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2502124	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5287194

1

T1

11410

T2

10

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30023	1			T1	55		T2	1		T5	5
valid_sources[0x01]	28920	1			T1	55		T4	294		T5	3
valid_sources[0x02]	30382	1			T1	48		T5	4		T7	1
valid_sources[0x03]	30198	1			T1	51		T4	1053		T5	4
valid_sources[0x04]	28452	1			T1	70		T4	16		T5	4
valid_sources[0x05]	28841	1			T1	60		T4	1		T5	2
valid_sources[0x06]	27943	1			T1	49		T5	1		T7	19
valid_sources[0x07]	33808	1			T1	40		T5	6		T11	3
valid_sources[0x08]	29896	1			T1	60		T4	1680		T5	5
valid_sources[0x09]	27308	1			T1	53		T5	1		T11	9
valid_sources[0x0a]	33998	1			T1	50		T5	4		T9	1
valid_sources[0x0b]	27901	1			T1	43		T5	4		T7	1
valid_sources[0x0c]	32469	1			T1	43		T4	1		T5	6
valid_sources[0x0d]	29551	1			T1	53		T5	8		T7	3
valid_sources[0x0e]	30123	1			T1	34		T5	7		T7	388
valid_sources[0x0f]	28788	1			T1	50		T5	4		T11	7
valid_sources[0x10]	29568	1			T1	52		T4	1		T5	6
valid_sources[0x11]	33515	1			T1	37		T4	416		T5	3
valid_sources[0x12]	28808	1			T1	67		T5	4		T9	1
valid_sources[0x13]	31740	1			T1	52		T5	1		T9	2
valid_sources[0x14]	30743	1			T1	42		T5	6		T9	1
valid_sources[0x15]	36066	1			T1	47		T2	1		T4	610
valid_sources[0x16]	28944	1			T1	49		T5	3		T9	1
valid_sources[0x17]	33124	1			T1	43		T5	4		T11	5
valid_sources[0x18]	29195	1			T1	45		T5	3		T7	487
valid_sources[0x19]	28426	1			T1	57		T5	10		T11	2
valid_sources[0x1a]	29616	1			T1	73		T4	1		T5	6
valid_sources[0x1b]	32497	1			T1	40		T2	1		T4	1254
valid_sources[0x1c]	27745	1			T1	51		T5	8		T9	1
valid_sources[0x1d]	29941	1			T1	54		T5	2		T9	1
valid_sources[0x1e]	28414	1			T1	45		T5	6		T9	1
valid_sources[0x1f]	34395	1			T1	50		T5	3		T9	1
valid_sources[0x20]	30813	1			T1	47		T5	5		T7	3
valid_sources[0x21]	32765	1			T1	52		T5	2		T7	2
valid_sources[0x22]	32007	1			T1	56		T5	3		T7	2
valid_sources[0x23]	27714	1			T1	48		T4	3		T5	4
valid_sources[0x24]	35296	1			T1	43		T4	2		T5	4
valid_sources[0x25]	29302	1			T1	38		T5	2		T9	3
valid_sources[0x26]	28437	1			T1	50		T5	3		T9	1
valid_sources[0x27]	33243	1			T1	47		T5	1		T11	1
valid_sources[0x28]	27891	1			T1	39		T5	3		T7	2
valid_sources[0x29]	34464	1			T1	45		T5	4		T7	79
valid_sources[0x2a]	45762	1			T1	66		T4	1		T5	4
valid_sources[0x2b]	28251	1			T1	56		T5	1		T11	5
valid_sources[0x2c]	32096	1			T1	59		T4	1		T5	8
valid_sources[0x2d]	29961	1			T1	59		T5	2		T7	240
valid_sources[0x2e]	31765	1			T1	52		T4	1		T5	2
valid_sources[0x2f]	27970	1			T1	54		T5	6		T7	2
valid_sources[0x30]	31631	1			T1	58		T5	7		T9	2
valid_sources[0x31]	30938	1			T1	59		T5	2		T9	1
valid_sources[0x32]	29067	1			T1	31		T5	5		T9	1
valid_sources[0x33]	29222	1			T1	58		T4	129		T5	2
valid_sources[0x34]	28397	1			T1	54		T5	2		T9	2
valid_sources[0x35]	27438	1			T1	50		T5	3		T7	3
valid_sources[0x36]	34865	1			T1	53		T4	1		T5	7
valid_sources[0x37]	34618	1			T1	60		T5	2		T7	73
valid_sources[0x38]	31294	1			T1	49		T5	2		T9	1
valid_sources[0x39]	33454	1			T1	57		T5	2		T11	9
valid_sources[0x3a]	31468	1			T1	49		T5	7		T7	1
valid_sources[0x3b]	29486	1			T1	43		T5	7		T7	288
valid_sources[0x3c]	29168	1			T1	51		T5	5		T11	3
valid_sources[0x3d]	30982	1			T1	57		T7	10		T9	1
valid_sources[0x3e]	27265	1			T1	47		T5	5		T7	299
valid_sources[0x3f]	29360	1			T1	49		T5	2		T7	1
valid_sources[0x40]	30864	1			T1	52		T5	2		T9	2
valid_sources[0x41]	28200	1			T1	61		T5	6		T11	6
valid_sources[0x42]	31401	1			T1	66		T4	1		T5	6
valid_sources[0x43]	27626	1			T1	62		T5	3		T9	2
valid_sources[0x44]	28367	1			T1	43		T5	3		T11	4
valid_sources[0x45]	27906	1			T1	50		T4	1		T5	7
valid_sources[0x46]	31070	1			T1	36		T4	1		T5	3
valid_sources[0x47]	29177	1			T1	45		T5	2		T11	4
valid_sources[0x48]	30413	1			T1	58		T7	90		T9	3
valid_sources[0x49]	28083	1			T1	54		T5	2		T7	1
valid_sources[0x4a]	30115	1			T1	50		T5	3		T7	88
valid_sources[0x4b]	27220	1			T1	42		T5	6		T11	2
valid_sources[0x4c]	50410	1			T1	57		T5	6		T11	2
valid_sources[0x4d]	33445	1			T1	36		T5	4		T11	4
valid_sources[0x4e]	32720	1			T1	48		T5	6		T11	4
valid_sources[0x4f]	31021	1			T1	33		T5	3		T7	1
valid_sources[0x50]	31730	1			T1	62		T4	1		T5	1
valid_sources[0x51]	38935	1			T1	50		T5	6		T7	1
valid_sources[0x52]	28215	1			T1	46		T5	5		T9	2
valid_sources[0x53]	31823	1			T1	41		T4	3		T5	4
valid_sources[0x54]	30509	1			T1	58		T5	1		T9	1
valid_sources[0x55]	27891	1			T1	49		T5	7		T11	5
valid_sources[0x56]	32050	1			T1	45		T5	4		T11	5
valid_sources[0x57]	28958	1			T1	60		T5	2		T11	4
valid_sources[0x58]	30844	1			T1	45		T5	3		T7	5
valid_sources[0x59]	25716	1			T1	42		T5	4		T9	2
valid_sources[0x5a]	32788	1			T1	69		T9	1		T11	2
valid_sources[0x5b]	26787	1			T1	57		T5	2		T9	1
valid_sources[0x5c]	30493	1			T1	51		T5	4		T11	2
valid_sources[0x5d]	29267	1			T1	62		T5	6		T9	2
valid_sources[0x5e]	28900	1			T1	43		T5	1		T11	4
valid_sources[0x5f]	26936	1			T1	54		T5	1		T7	7
valid_sources[0x60]	30146	1			T1	43		T9	2		T11	1
valid_sources[0x61]	27207	1			T1	55		T5	3		T11	5
valid_sources[0x62]	31635	1			T1	55		T5	4		T7	38
valid_sources[0x63]	31108	1			T1	52		T5	7		T7	1
valid_sources[0x64]	26084	1			T1	59		T5	4		T11	4
valid_sources[0x65]	30588	1			T1	42		T5	2		T11	6
valid_sources[0x66]	28954	1			T1	54		T5	1		T7	16
valid_sources[0x67]	27508	1			T1	39		T5	1		T7	25
valid_sources[0x68]	31712	1			T1	54		T5	2		T7	1
valid_sources[0x69]	27557	1			T1	64		T5	7		T7	462
valid_sources[0x6a]	27210	1			T1	53		T7	84		T11	6
valid_sources[0x6b]	30884	1			T1	55		T5	3		T9	1
valid_sources[0x6c]	31082	1			T1	55		T5	3		T9	3
valid_sources[0x6d]	32052	1			T1	41		T4	1		T5	2
valid_sources[0x6e]	31411	1			T1	48		T5	4		T7	1
valid_sources[0x6f]	30949	1			T1	63		T5	4		T7	1
valid_sources[0x70]	28232	1			T1	48		T5	6		T9	2
valid_sources[0x71]	31541	1			T1	72		T5	6		T7	2
valid_sources[0x72]	27882	1			T1	57		T2	2		T5	3
valid_sources[0x73]	30507	1			T1	46		T5	3		T9	3
valid_sources[0x74]	30245	1			T1	64		T4	1		T5	4
valid_sources[0x75]	29031	1			T1	52		T4	2		T5	5
valid_sources[0x76]	33675	1			T1	46		T5	2		T7	20
valid_sources[0x77]	31106	1			T1	52		T5	1		T7	447
valid_sources[0x78]	29030	1			T1	53		T2	1		T5	4
valid_sources[0x79]	29669	1			T1	46		T4	546		T5	4
valid_sources[0x7a]	28037	1			T1	42		T5	2		T7	6
valid_sources[0x7b]	31171	1			T1	54		T5	6		T9	2
valid_sources[0x7c]	28474	1			T1	57		T9	2		T11	5
valid_sources[0x7d]	30107	1			T1	54		T4	1		T5	2
valid_sources[0x7e]	27747	1			T1	61		T2	2		T5	2
valid_sources[0x7f]	27257	1			T1	42		T5	6		T11	7
valid_sources[0x80]	29272	1			T1	46		T4	1		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1070818

1

T1

2237

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1611545

1

T1

4407

T2

6

T4

3983

values[0x1]

all_enables

biggest_size

1586611

1

T1

4343

T2

3

T3

2