Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3539078

1

T1

2089

T2

1

T3

2

full_word

4268013

1

T1

10987

T2

10

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7806651	1			T1	13076		T2	11		T3	5
auto[TlIntgErrCmd]	133	1			T101	1		T102	6		T104	15
auto[TlIntgErrData]	157	1			T101	3		T102	10		T104	8
auto[TlIntgErrBoth]	150	1			T101	6		T102	14		T104	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4269036

1

T1

4281

T2

1

T3

1

auto[1]

3538055

1

T1

8795

T2

10

T3

4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3197961	1			T1	2044		T4	462		T5	3
auto[TlIntgErrNone]	partial	auto[1]	340718	1			T1	45		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1070878	1			T1	2237		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3197094	1			T1	8750		T2	9		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T101	1		T102	2		T104	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T102	4		T104	10		T155	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T104	1		T173	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T104	1		T174	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	74	1			T101	2		T102	7		T104	1
auto[TlIntgErrData]	partial	auto[1]	68	1			T101	1		T102	2		T104	7
auto[TlIntgErrData]	full_word	auto[0]	11	1			T155	2		T172	2		T175	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T102	1		T172	1		T176	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T101	3		T102	5		T104	3
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T101	2		T102	8		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T102	1		T104	1		T155	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T101	1		T172	2		T174	2