Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	452460268	2921020	0	0
DepthKnown_A	452460268	452324891	0	0
RvalidKnown_A	452460268	452324891	0	0
WreadyKnown_A	452460268	452324891	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2921020	0	0
T1	259393	14137	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	10812	0	0
T5	798416	1663	0	0
T6	10482	0	0	0
T7	107066	4158	0	0
T8	58855	832	0	0
T9	2133	100	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6654	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	452460268	3053010	0	0
DepthKnown_A	452460268	452324891	0	0
RvalidKnown_A	452460268	452324891	0	0
WreadyKnown_A	452460268	452324891	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	3053010	0	0
T1	259393	8320	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7488	0	0
T5	798416	832	0	0
T6	10482	0	0	0
T7	107066	2496	0	0
T8	58855	832	0	0
T9	2133	100	0	0
T10	36159	832	0	0
T11	0	2604	0	0
T12	0	12138	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	452460268	193002	0	0
DepthKnown_A	452460268	452324891	0	0
RvalidKnown_A	452460268	452324891	0	0
WreadyKnown_A	452460268	452324891	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	193002	0	0
T1	259393	129	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	193	0	0
T5	798416	0	0	0
T6	10482	49	0	0
T7	107066	512	0	0
T8	58855	0	0	0
T9	2133	100	0	0
T10	36159	0	0	0
T12	0	791	0	0
T29	0	328	0	0
T42	0	100	0	0
T44	0	234	0	0
T45	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	452460268	407779	0	0
DepthKnown_A	452460268	452324891	0	0
RvalidKnown_A	452460268	452324891	0	0
WreadyKnown_A	452460268	452324891	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	407779	0	0
T1	259393	129	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	193	0	0
T5	798416	0	0	0
T6	10482	49	0	0
T7	107066	512	0	0
T8	58855	0	0	0
T9	2133	100	0	0
T10	36159	0	0	0
T12	0	2649	0	0
T29	0	328	0	0
T42	0	100	0	0
T44	0	1029	0	0
T45	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	452460268	6068847	0	0
DepthKnown_A	452460268	452324891	0	0
RvalidKnown_A	452460268	452324891	0	0
WreadyKnown_A	452460268	452324891	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	6068847	0	0
T1	259393	4628	0	0
T2	2626	11	0	0
T3	2304	5	0	0
T4	266667	1271	0	0
T5	798416	69	0	0
T6	10482	744	0	0
T7	107066	3639	0	0
T8	58855	53	0	0
T9	2133	1	0	0
T10	36159	1800	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	452460268	11948677	0	0
DepthKnown_A	452460268	452324891	0	0
RvalidKnown_A	452460268	452324891	0	0
WreadyKnown_A	452460268	452324891	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	11948677	0	0
T1	259393	4627	0	0
T2	2626	55	0	0
T3	2304	25	0	0
T4	266667	1268	0	0
T5	798416	166	0	0
T6	10482	744	0	0
T7	107066	3602	0	0
T8	58855	53	0	0
T9	2133	1	0	0
T10	36159	1800	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	452324891	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0