Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T12
1	0	Covered	T6,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T6,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	755074288	601371033	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	755074288	3838718	0	0
GntImpliesValid_A	755074288	3838718	0	0
GrantKnown_A	755074288	601371033	0	0
IdxKnown_A	755074288	601371033	0	0
IndexIsCorrect_A	755074288	3838718	0	0
LockArbDecision_A	755074288	0	0	0
NoReadyValidNoGrant_A	755074288	0	0	0
ReadyAndValidImplyGrant_A	755074288	3838718	0	0
ReqAndReadyImplyGrant_A	755074288	3838718	0	0
ReqImpliesValid_A	755074288	3838718	0	0
ReqStaysHighUntilGranted0_M	755074288	0	0	0
RoundRobin_A	755074288	4	0	975
ValidKnown_A	755074288	601371033	0	0
gen_data_port_assertion.DataFlow_A	755074288	3838718	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	601371033	0	0
T1	897807	896392	0	0
T2	3058	2758	0	0
T3	3040	2316	0	0
T4	1554095	907668	0	0
T5	1063124	930529	0	0
T6	18930	14644	0	0
T7	742046	421738	0	0
T8	154537	106202	0	0
T9	2133	2055	0	0
T10	51503	43326	0	0
T11	26552	13024	0	0
T12	483119	478114	0	0
T13	0	56592	0	0
T14	0	22542	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	3838718	0	0
T1	897807	11070	0	0
T2	2842	0	0	0
T3	2672	0	0	0
T4	910381	9763	0	0
T5	930770	832	0	0
T6	18930	359	0	0
T7	742046	6358	0	0
T8	154537	832	0	0
T9	2133	200	0	0
T10	51503	832	0	0
T11	26552	832	0	0
T12	483119	16942	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T25	0	643	0	0
T26	0	6261	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2489	0	0
T38	0	1508	0	0
T44	0	1719	0	0
T45	0	258	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	6726	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	3838718	0	0
T1	897807	11070	0	0
T2	2842	0	0	0
T3	2672	0	0	0
T4	910381	9763	0	0
T5	930770	832	0	0
T6	18930	359	0	0
T7	742046	6358	0	0
T8	154537	832	0	0
T9	2133	200	0	0
T10	51503	832	0	0
T11	26552	832	0	0
T12	483119	16942	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T25	0	643	0	0
T26	0	6261	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2489	0	0
T38	0	1508	0	0
T44	0	1719	0	0
T45	0	258	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	6726	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	601371033	0	0
T1	897807	896392	0	0
T2	3058	2758	0	0
T3	3040	2316	0	0
T4	1554095	907668	0	0
T5	1063124	930529	0	0
T6	18930	14644	0	0
T7	742046	421738	0	0
T8	154537	106202	0	0
T9	2133	2055	0	0
T10	51503	43326	0	0
T11	26552	13024	0	0
T12	483119	478114	0	0
T13	0	56592	0	0
T14	0	22542	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	601371033	0	0
T1	897807	896392	0	0
T2	3058	2758	0	0
T3	3040	2316	0	0
T4	1554095	907668	0	0
T5	1063124	930529	0	0
T6	18930	14644	0	0
T7	742046	421738	0	0
T8	154537	106202	0	0
T9	2133	2055	0	0
T10	51503	43326	0	0
T11	26552	13024	0	0
T12	483119	478114	0	0
T13	0	56592	0	0
T14	0	22542	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	3838718	0	0
T1	897807	11070	0	0
T2	2842	0	0	0
T3	2672	0	0	0
T4	910381	9763	0	0
T5	930770	832	0	0
T6	18930	359	0	0
T7	742046	6358	0	0
T8	154537	832	0	0
T9	2133	200	0	0
T10	51503	832	0	0
T11	26552	832	0	0
T12	483119	16942	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T25	0	643	0	0
T26	0	6261	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2489	0	0
T38	0	1508	0	0
T44	0	1719	0	0
T45	0	258	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	6726	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	3838718	0	0
T1	897807	11070	0	0
T2	2842	0	0	0
T3	2672	0	0	0
T4	910381	9763	0	0
T5	930770	832	0	0
T6	18930	359	0	0
T7	742046	6358	0	0
T8	154537	832	0	0
T9	2133	200	0	0
T10	51503	832	0	0
T11	26552	832	0	0
T12	483119	16942	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T25	0	643	0	0
T26	0	6261	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2489	0	0
T38	0	1508	0	0
T44	0	1719	0	0
T45	0	258	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	6726	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	3838718	0	0
T1	897807	11070	0	0
T2	2842	0	0	0
T3	2672	0	0	0
T4	910381	9763	0	0
T5	930770	832	0	0
T6	18930	359	0	0
T7	742046	6358	0	0
T8	154537	832	0	0
T9	2133	200	0	0
T10	51503	832	0	0
T11	26552	832	0	0
T12	483119	16942	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T25	0	643	0	0
T26	0	6261	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2489	0	0
T38	0	1508	0	0
T44	0	1719	0	0
T45	0	258	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	6726	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	3838718	0	0
T1	897807	11070	0	0
T2	2842	0	0	0
T3	2672	0	0	0
T4	910381	9763	0	0
T5	930770	832	0	0
T6	18930	359	0	0
T7	742046	6358	0	0
T8	154537	832	0	0
T9	2133	200	0	0
T10	51503	832	0	0
T11	26552	832	0	0
T12	483119	16942	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T25	0	643	0	0
T26	0	6261	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2489	0	0
T38	0	1508	0	0
T44	0	1719	0	0
T45	0	258	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	6726	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	4	0	975
T58	955949	1	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	6628	0	0	1
T63	19371	0	0	1
T64	360403	0	0	1
T65	592276	0	0	1
T66	956	0	0	1
T67	10118	0	0	1
T68	93467	0	0	1
T69	2953	0	0	1
T70	909540	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	601371033	0	0
T1	897807	896392	0	0
T2	3058	2758	0	0
T3	3040	2316	0	0
T4	1554095	907668	0	0
T5	1063124	930529	0	0
T6	18930	14644	0	0
T7	742046	421738	0	0
T8	154537	106202	0	0
T9	2133	2055	0	0
T10	51503	43326	0	0
T11	26552	13024	0	0
T12	483119	478114	0	0
T13	0	56592	0	0
T14	0	22542	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755074288	3838718	0	0
T1	897807	11070	0	0
T2	2842	0	0	0
T3	2672	0	0	0
T4	910381	9763	0	0
T5	930770	832	0	0
T6	18930	359	0	0
T7	742046	6358	0	0
T8	154537	832	0	0
T9	2133	200	0	0
T10	51503	832	0	0
T11	26552	832	0	0
T12	483119	16942	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T25	0	643	0	0
T26	0	6261	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2489	0	0
T38	0	1508	0	0
T44	0	1719	0	0
T45	0	258	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	6726	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T12
1	0	Covered	T6,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T6,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152274351	28829679	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	152274351	638189	0	0
GntImpliesValid_A	152274351	638189	0	0
GrantKnown_A	152274351	28829679	0	0
IdxKnown_A	152274351	28829679	0	0
IndexIsCorrect_A	152274351	638189	0	0
LockArbDecision_A	152274351	0	0	0
NoReadyValidNoGrant_A	152274351	0	0	0
ReadyAndValidImplyGrant_A	152274351	638189	0	0
ReqAndReadyImplyGrant_A	152274351	638189	0	0
ReqImpliesValid_A	152274351	638189	0	0
ReqStaysHighUntilGranted0_M	152274351	0	0	0
RoundRobin_A	152274351	0	0	0
ValidKnown_A	152274351	28829679	0	0
gen_data_port_assertion.DataFlow_A	152274351	638189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	28829679	0	0
T2	216	216	0	0
T3	368	72	0	0
T4	643714	0	0	0
T5	132354	0	0	0
T6	4224	4224	0	0
T7	317490	206408	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	55576	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	638189	0	0
T6	4224	251	0	0
T7	317490	2264	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	2411	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T26	0	5996	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2227	0	0
T38	0	1508	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	5683	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	638189	0	0
T6	4224	251	0	0
T7	317490	2264	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	2411	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T26	0	5996	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2227	0	0
T38	0	1508	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	5683	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	28829679	0	0
T2	216	216	0	0
T3	368	72	0	0
T4	643714	0	0	0
T5	132354	0	0	0
T6	4224	4224	0	0
T7	317490	206408	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	55576	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	28829679	0	0
T2	216	216	0	0
T3	368	72	0	0
T4	643714	0	0	0
T5	132354	0	0	0
T6	4224	4224	0	0
T7	317490	206408	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	55576	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	638189	0	0
T6	4224	251	0	0
T7	317490	2264	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	2411	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T26	0	5996	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2227	0	0
T38	0	1508	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	5683	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	638189	0	0
T6	4224	251	0	0
T7	317490	2264	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	2411	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T26	0	5996	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2227	0	0
T38	0	1508	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	5683	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	638189	0	0
T6	4224	251	0	0
T7	317490	2264	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	2411	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T26	0	5996	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2227	0	0
T38	0	1508	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	5683	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	638189	0	0
T6	4224	251	0	0
T7	317490	2264	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	2411	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T26	0	5996	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2227	0	0
T38	0	1508	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	5683	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	28829679	0	0
T2	216	216	0	0
T3	368	72	0	0
T4	643714	0	0	0
T5	132354	0	0	0
T6	4224	4224	0	0
T7	317490	206408	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	55576	0	0
T26	0	132296	0	0
T29	0	111296	0	0
T30	0	90736	0	0
T31	0	86440	0	0
T33	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	638189	0	0
T6	4224	251	0	0
T7	317490	2264	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	483119	2411	0	0
T13	57490	0	0	0
T14	23102	0	0	0
T26	0	5996	0	0
T29	114444	1873	0	0
T31	0	2191	0	0
T34	0	2227	0	0
T38	0	1508	0	0
T46	0	3419	0	0
T50	17408	0	0	0
T57	0	5683	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152274351	122103399	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	152274351	890584	0	0
GntImpliesValid_A	152274351	890584	0	0
GrantKnown_A	152274351	122103399	0	0
IdxKnown_A	152274351	122103399	0	0
IndexIsCorrect_A	152274351	890584	0	0
LockArbDecision_A	152274351	0	0	0
NoReadyValidNoGrant_A	152274351	0	0	0
ReadyAndValidImplyGrant_A	152274351	890584	0	0
ReqAndReadyImplyGrant_A	152274351	890584	0	0
ReqImpliesValid_A	152274351	890584	0	0
ReqStaysHighUntilGranted0_M	152274351	0	0	0
RoundRobin_A	152274351	0	0	0
ValidKnown_A	152274351	122103399	0	0
gen_data_port_assertion.DataFlow_A	152274351	890584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	122103399	0	0
T1	638414	637005	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	641062	0	0
T5	132354	132188	0	0
T6	4224	0	0	0
T7	317490	108364	0	0
T8	47841	47446	0	0
T10	7672	7264	0	0
T11	13276	13024	0	0
T12	0	422538	0	0
T13	0	56592	0	0
T14	0	22542	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	890584	0	0
T1	638414	2607	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	2068	0	0
T5	132354	0	0	0
T6	4224	0	0	0
T7	317490	423	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	0	8146	0	0
T25	0	643	0	0
T26	0	265	0	0
T34	0	262	0	0
T44	0	1719	0	0
T45	0	258	0	0
T57	0	1043	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	890584	0	0
T1	638414	2607	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	2068	0	0
T5	132354	0	0	0
T6	4224	0	0	0
T7	317490	423	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	0	8146	0	0
T25	0	643	0	0
T26	0	265	0	0
T34	0	262	0	0
T44	0	1719	0	0
T45	0	258	0	0
T57	0	1043	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	122103399	0	0
T1	638414	637005	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	641062	0	0
T5	132354	132188	0	0
T6	4224	0	0	0
T7	317490	108364	0	0
T8	47841	47446	0	0
T10	7672	7264	0	0
T11	13276	13024	0	0
T12	0	422538	0	0
T13	0	56592	0	0
T14	0	22542	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	122103399	0	0
T1	638414	637005	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	641062	0	0
T5	132354	132188	0	0
T6	4224	0	0	0
T7	317490	108364	0	0
T8	47841	47446	0	0
T10	7672	7264	0	0
T11	13276	13024	0	0
T12	0	422538	0	0
T13	0	56592	0	0
T14	0	22542	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	890584	0	0
T1	638414	2607	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	2068	0	0
T5	132354	0	0	0
T6	4224	0	0	0
T7	317490	423	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	0	8146	0	0
T25	0	643	0	0
T26	0	265	0	0
T34	0	262	0	0
T44	0	1719	0	0
T45	0	258	0	0
T57	0	1043	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	890584	0	0
T1	638414	2607	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	2068	0	0
T5	132354	0	0	0
T6	4224	0	0	0
T7	317490	423	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	0	8146	0	0
T25	0	643	0	0
T26	0	265	0	0
T34	0	262	0	0
T44	0	1719	0	0
T45	0	258	0	0
T57	0	1043	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	890584	0	0
T1	638414	2607	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	2068	0	0
T5	132354	0	0	0
T6	4224	0	0	0
T7	317490	423	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	0	8146	0	0
T25	0	643	0	0
T26	0	265	0	0
T34	0	262	0	0
T44	0	1719	0	0
T45	0	258	0	0
T57	0	1043	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	890584	0	0
T1	638414	2607	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	2068	0	0
T5	132354	0	0	0
T6	4224	0	0	0
T7	317490	423	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	0	8146	0	0
T25	0	643	0	0
T26	0	265	0	0
T34	0	262	0	0
T44	0	1719	0	0
T45	0	258	0	0
T57	0	1043	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	122103399	0	0
T1	638414	637005	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	641062	0	0
T5	132354	132188	0	0
T6	4224	0	0	0
T7	317490	108364	0	0
T8	47841	47446	0	0
T10	7672	7264	0	0
T11	13276	13024	0	0
T12	0	422538	0	0
T13	0	56592	0	0
T14	0	22542	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152274351	890584	0	0
T1	638414	2607	0	0
T2	216	0	0	0
T3	368	0	0	0
T4	643714	2068	0	0
T5	132354	0	0	0
T6	4224	0	0	0
T7	317490	423	0	0
T8	47841	0	0	0
T10	7672	0	0	0
T11	13276	0	0	0
T12	0	8146	0	0
T25	0	643	0	0
T26	0	265	0	0
T34	0	262	0	0
T44	0	1719	0	0
T45	0	258	0	0
T57	0	1043	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	450525586	450437955	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	450525586	2309945	0	0
GntImpliesValid_A	450525586	2309945	0	0
GrantKnown_A	450525586	450437955	0	0
IdxKnown_A	450525586	450437955	0	0
IndexIsCorrect_A	450525586	2309945	0	0
LockArbDecision_A	450525586	0	0	0
NoReadyValidNoGrant_A	450525586	0	0	0
ReadyAndValidImplyGrant_A	450525586	2309945	0	0
ReqAndReadyImplyGrant_A	450525586	2309945	0	0
ReqImpliesValid_A	450525586	2309945	0	0
ReqStaysHighUntilGranted0_M	450525586	0	0	0
RoundRobin_A	450525586	4	0	975
ValidKnown_A	450525586	450437955	0	0
gen_data_port_assertion.DataFlow_A	450525586	2309945	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	450437955	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	2309945	0	0
T1	259393	8463	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7695	0	0
T5	798416	832	0	0
T6	10482	108	0	0
T7	107066	3671	0	0
T8	58855	832	0	0
T9	2133	200	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6385	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	2309945	0	0
T1	259393	8463	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7695	0	0
T5	798416	832	0	0
T6	10482	108	0	0
T7	107066	3671	0	0
T8	58855	832	0	0
T9	2133	200	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6385	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	450437955	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	450437955	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	2309945	0	0
T1	259393	8463	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7695	0	0
T5	798416	832	0	0
T6	10482	108	0	0
T7	107066	3671	0	0
T8	58855	832	0	0
T9	2133	200	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6385	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	2309945	0	0
T1	259393	8463	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7695	0	0
T5	798416	832	0	0
T6	10482	108	0	0
T7	107066	3671	0	0
T8	58855	832	0	0
T9	2133	200	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6385	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	2309945	0	0
T1	259393	8463	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7695	0	0
T5	798416	832	0	0
T6	10482	108	0	0
T7	107066	3671	0	0
T8	58855	832	0	0
T9	2133	200	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6385	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	2309945	0	0
T1	259393	8463	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7695	0	0
T5	798416	832	0	0
T6	10482	108	0	0
T7	107066	3671	0	0
T8	58855	832	0	0
T9	2133	200	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6385	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	4	0	975
T58	955949	1	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	6628	0	0	1
T63	19371	0	0	1
T64	360403	0	0	1
T65	592276	0	0	1
T66	956	0	0	1
T67	10118	0	0	1
T68	93467	0	0	1
T69	2953	0	0	1
T70	909540	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	450437955	0	0
T1	259393	259387	0	0
T2	2626	2542	0	0
T3	2304	2244	0	0
T4	266667	266606	0	0
T5	798416	798341	0	0
T6	10482	10420	0	0
T7	107066	106966	0	0
T8	58855	58756	0	0
T9	2133	2055	0	0
T10	36159	36062	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450525586	2309945	0	0
T1	259393	8463	0	0
T2	2626	0	0	0
T3	2304	0	0	0
T4	266667	7695	0	0
T5	798416	832	0	0
T6	10482	108	0	0
T7	107066	3671	0	0
T8	58855	832	0	0
T9	2133	200	0	0
T10	36159	832	0	0
T11	0	832	0	0
T12	0	6385	0	0