Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	452460268	3586	0	0
addr_swap_data_rd_A	452460268	1186	0	0
addr_swap_mask_rd_A	452460268	1230	0	0
cfg_rd_A	452460268	1454	0	0
cmd_filter_0_rd_A	452460268	4637	0	0
cmd_filter_1_rd_A	452460268	4985	0	0
cmd_filter_2_rd_A	452460268	5212	0	0
cmd_filter_3_rd_A	452460268	5727	0	0
cmd_filter_4_rd_A	452460268	6195	0	0
cmd_filter_5_rd_A	452460268	5241	0	0
cmd_filter_6_rd_A	452460268	5447	0	0
cmd_filter_7_rd_A	452460268	4929	0	0
cmd_info_0_rd_A	452460268	2532	0	0
cmd_info_10_rd_A	452460268	2722	0	0
cmd_info_11_rd_A	452460268	2832	0	0
cmd_info_12_rd_A	452460268	2877	0	0
cmd_info_13_rd_A	452460268	2587	0	0
cmd_info_14_rd_A	452460268	2968	0	0
cmd_info_15_rd_A	452460268	2852	0	0
cmd_info_16_rd_A	452460268	2808	0	0
cmd_info_17_rd_A	452460268	2846	0	0
cmd_info_18_rd_A	452460268	2799	0	0
cmd_info_19_rd_A	452460268	3008	0	0
cmd_info_1_rd_A	452460268	2596	0	0
cmd_info_20_rd_A	452460268	2664	0	0
cmd_info_21_rd_A	452460268	2812	0	0
cmd_info_22_rd_A	452460268	3071	0	0
cmd_info_23_rd_A	452460268	3003	0	0
cmd_info_2_rd_A	452460268	2526	0	0
cmd_info_3_rd_A	452460268	2627	0	0
cmd_info_4_rd_A	452460268	2851	0	0
cmd_info_5_rd_A	452460268	2694	0	0
cmd_info_6_rd_A	452460268	3160	0	0
cmd_info_7_rd_A	452460268	2579	0	0
cmd_info_8_rd_A	452460268	2885	0	0
cmd_info_9_rd_A	452460268	2643	0	0
cmd_info_en4b_rd_A	452460268	1210	0	0
cmd_info_ex4b_rd_A	452460268	1272	0	0
cmd_info_wrdi_rd_A	452460268	1380	0	0
cmd_info_wren_rd_A	452460268	1298	0	0
intercept_en_rd_A	452460268	1750	0	0
intr_enable_rd_A	452460268	2804	0	0
jedec_cc_rd_A	452460268	1352	0	0
jedec_id_rd_A	452460268	1257	0	0
mailbox_addr_rd_A	452460268	1118	0	0
payload_swap_data_rd_A	452460268	1102	0	0
payload_swap_mask_rd_A	452460268	1071	0	0
read_threshold_rd_A	452460268	1155	0	0
tpm_access_0_rd_A	452460268	1531	0	0
tpm_access_1_rd_A	452460268	1067	0	0
tpm_cfg_rd_A	452460268	1616	0	0
tpm_did_vid_rd_A	452460268	1420	0	0
tpm_int_enable_rd_A	452460268	1182	0	0
tpm_int_status_rd_A	452460268	1162	0	0
tpm_int_vector_rd_A	452460268	1182	0	0
tpm_intf_capability_rd_A	452460268	1183	0	0
tpm_rid_rd_A	452460268	1101	0	0
tpm_sts_rd_A	452460268	1248	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	3586	0	0
T98	8474	45	0	0
T99	12619	3	0	0
T100	8110	68	0	0
T102	32692	4	0	0
T103	11043	166	0	0
T104	28970	2	0	0
T105	12601	5	0	0
T115	9590	2	0	0
T116	10463	1	0	0
T117	4150	5	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1186	0	0
T88	3468	6	0	0
T105	12601	3	0	0
T116	10463	18	0	0
T121	3456	2	0	0
T139	13977	64	0	0
T142	7888	12	0	0
T151	7238	35	0	0
T152	18711	29	0	0
T153	20393	34	0	0
T154	5688	13	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1230	0	0
T88	3468	11	0	0
T105	12601	18	0	0
T116	10463	21	0	0
T121	3456	4	0	0
T139	13977	77	0	0
T142	7888	16	0	0
T151	7238	6	0	0
T152	18711	64	0	0
T153	20393	66	0	0
T154	5688	15	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1454	0	0
T88	3468	15	0	0
T105	12601	29	0	0
T116	10463	21	0	0
T121	3456	2	0	0
T139	13977	43	0	0
T142	7888	3	0	0
T151	7238	22	0	0
T152	18711	93	0	0
T153	20393	50	0	0
T154	5688	8	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	4637	0	0
T88	3468	4	0	0
T105	12601	149	0	0
T116	10463	133	0	0
T121	3456	1	0	0
T139	13977	50	0	0
T142	7888	57	0	0
T151	7238	26	0	0
T152	18711	51	0	0
T153	20393	74	0	0
T154	5688	16	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	4985	0	0
T88	3468	2	0	0
T105	12601	5	0	0
T116	10463	215	0	0
T121	3456	1	0	0
T139	13977	51	0	0
T142	7888	42	0	0
T151	7238	23	0	0
T152	18711	79	0	0
T153	20393	36	0	0
T154	5688	5	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	5212	0	0
T88	3468	5	0	0
T105	12601	119	0	0
T116	10463	133	0	0
T139	13977	25	0	0
T142	7888	39	0	0
T151	7238	26	0	0
T152	18711	11	0	0
T153	20393	53	0	0
T154	5688	138	0	0
T155	65262	604	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	5727	0	0
T88	3468	5	0	0
T105	12601	11	0	0
T116	10463	289	0	0
T121	3456	7	0	0
T139	13977	31	0	0
T142	7888	13	0	0
T151	7238	29	0	0
T152	18711	68	0	0
T153	20393	88	0	0
T154	5688	143	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	6195	0	0
T88	3468	9	0	0
T105	12601	78	0	0
T116	10463	227	0	0
T121	3456	128	0	0
T139	13977	33	0	0
T142	7888	31	0	0
T151	7238	12	0	0
T152	18711	50	0	0
T153	20393	52	0	0
T154	5688	9	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	5241	0	0
T88	3468	6	0	0
T105	12601	108	0	0
T106	17232	2	0	0
T116	10463	130	0	0
T121	3456	6	0	0
T139	13977	12	0	0
T142	7888	6	0	0
T151	7238	37	0	0
T152	18711	34	0	0
T153	20393	74	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	5447	0	0
T88	3468	5	0	0
T98	8474	6	0	0
T105	12601	115	0	0
T116	10463	14	0	0
T121	3456	7	0	0
T139	13977	57	0	0
T142	7888	30	0	0
T151	7238	21	0	0
T152	18711	46	0	0
T153	20393	42	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	4929	0	0
T88	3468	15	0	0
T105	12601	1	0	0
T116	10463	232	0	0
T121	3456	124	0	0
T139	13977	18	0	0
T142	7888	9	0	0
T151	7238	13	0	0
T152	18711	65	0	0
T153	20393	41	0	0
T154	5688	122	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2532	0	0
T88	3468	6	0	0
T105	12601	13	0	0
T116	10463	14	0	0
T121	3456	6	0	0
T139	13977	62	0	0
T142	7888	21	0	0
T151	7238	9	0	0
T152	18711	32	0	0
T153	20393	45	0	0
T154	5688	65	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2722	0	0
T88	3468	11	0	0
T105	12601	72	0	0
T116	10463	107	0	0
T121	3456	44	0	0
T139	13977	5	0	0
T142	7888	30	0	0
T151	7238	29	0	0
T152	18711	87	0	0
T153	20393	41	0	0
T154	5688	62	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2832	0	0
T88	3468	6	0	0
T105	12601	39	0	0
T116	10463	79	0	0
T121	3456	31	0	0
T139	13977	73	0	0
T142	7888	18	0	0
T151	7238	40	0	0
T152	18711	54	0	0
T153	20393	62	0	0
T154	5688	40	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2877	0	0
T88	3468	4	0	0
T105	12601	33	0	0
T106	17232	7	0	0
T116	10463	62	0	0
T121	3456	2	0	0
T139	13977	35	0	0
T142	7888	33	0	0
T151	7238	35	0	0
T152	18711	65	0	0
T153	20393	87	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2587	0	0
T88	3468	1	0	0
T105	12601	61	0	0
T116	10463	51	0	0
T121	3456	5	0	0
T139	13977	72	0	0
T142	7888	18	0	0
T151	7238	30	0	0
T152	18711	49	0	0
T153	20393	42	0	0
T154	5688	6	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2968	0	0
T88	3468	9	0	0
T105	12601	80	0	0
T116	10463	13	0	0
T121	3456	51	0	0
T139	13977	8	0	0
T142	7888	3	0	0
T151	7238	44	0	0
T152	18711	71	0	0
T153	20393	100	0	0
T154	5688	11	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2852	0	0
T88	3468	3	0	0
T105	12601	46	0	0
T116	10463	60	0	0
T121	3456	6	0	0
T139	13977	40	0	0
T142	7888	11	0	0
T151	7238	22	0	0
T152	18711	48	0	0
T153	20393	33	0	0
T154	5688	54	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2808	0	0
T88	3468	5	0	0
T105	12601	72	0	0
T116	10463	9	0	0
T121	3456	54	0	0
T139	13977	40	0	0
T142	7888	20	0	0
T151	7238	24	0	0
T152	18711	65	0	0
T153	20393	36	0	0
T154	5688	64	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2846	0	0
T88	3468	11	0	0
T105	12601	112	0	0
T116	10463	78	0	0
T121	3456	69	0	0
T139	13977	65	0	0
T142	7888	29	0	0
T151	7238	13	0	0
T152	18711	69	0	0
T153	20393	49	0	0
T154	5688	7	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2799	0	0
T88	3468	6	0	0
T105	12601	5	0	0
T116	10463	56	0	0
T121	3456	52	0	0
T139	13977	4	0	0
T151	7238	14	0	0
T152	18711	87	0	0
T153	20393	68	0	0
T154	5688	13	0	0
T155	65262	342	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	3008	0	0
T88	3468	10	0	0
T105	12601	50	0	0
T116	10463	13	0	0
T121	3456	1	0	0
T139	13977	53	0	0
T142	7888	4	0	0
T151	7238	18	0	0
T152	18711	71	0	0
T153	20393	110	0	0
T154	5688	73	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2596	0	0
T88	3468	9	0	0
T105	12601	44	0	0
T116	10463	55	0	0
T121	3456	8	0	0
T139	13977	43	0	0
T142	7888	14	0	0
T151	7238	13	0	0
T152	18711	41	0	0
T153	20393	74	0	0
T154	5688	6	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2664	0	0
T88	3468	8	0	0
T105	12601	87	0	0
T106	17232	8	0	0
T116	10463	126	0	0
T121	3456	36	0	0
T139	13977	51	0	0
T142	7888	58	0	0
T151	7238	39	0	0
T152	18711	20	0	0
T153	20393	115	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2812	0	0
T88	3468	6	0	0
T105	12601	45	0	0
T116	10463	5	0	0
T121	3456	5	0	0
T139	13977	53	0	0
T142	7888	18	0	0
T151	7238	10	0	0
T152	18711	69	0	0
T153	20393	55	0	0
T154	5688	9	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	3071	0	0
T88	3468	13	0	0
T105	12601	74	0	0
T116	10463	13	0	0
T121	3456	75	0	0
T139	13977	28	0	0
T142	7888	17	0	0
T151	7238	14	0	0
T152	18711	94	0	0
T153	20393	56	0	0
T154	5688	49	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	3003	0	0
T88	3468	14	0	0
T105	12601	22	0	0
T116	10463	118	0	0
T121	3456	3	0	0
T139	13977	30	0	0
T142	7888	16	0	0
T152	18711	89	0	0
T153	20393	78	0	0
T154	5688	71	0	0
T155	65262	272	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2526	0	0
T88	3468	9	0	0
T105	12601	49	0	0
T116	10463	9	0	0
T121	3456	5	0	0
T139	13977	41	0	0
T142	7888	10	0	0
T151	7238	3	0	0
T152	18711	72	0	0
T153	20393	34	0	0
T154	5688	7	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2627	0	0
T88	3468	7	0	0
T105	12601	49	0	0
T116	10463	41	0	0
T121	3456	81	0	0
T139	13977	38	0	0
T142	7888	12	0	0
T151	7238	17	0	0
T152	18711	73	0	0
T153	20393	50	0	0
T154	5688	7	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2851	0	0
T88	3468	8	0	0
T105	12601	13	0	0
T116	10463	51	0	0
T121	3456	2	0	0
T139	13977	29	0	0
T142	7888	30	0	0
T151	7238	12	0	0
T152	18711	72	0	0
T153	20393	52	0	0
T154	5688	49	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2694	0	0
T88	3468	8	0	0
T105	12601	91	0	0
T116	10463	51	0	0
T121	3456	1	0	0
T139	13977	28	0	0
T142	7888	39	0	0
T151	7238	9	0	0
T152	18711	60	0	0
T153	20393	85	0	0
T154	5688	12	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	3160	0	0
T88	3468	3	0	0
T105	12601	74	0	0
T116	10463	66	0	0
T121	3456	8	0	0
T139	13977	48	0	0
T142	7888	9	0	0
T151	7238	39	0	0
T152	18711	120	0	0
T153	20393	73	0	0
T154	5688	29	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2579	0	0
T88	3468	5	0	0
T105	12601	32	0	0
T116	10463	80	0	0
T121	3456	44	0	0
T139	13977	64	0	0
T142	7888	26	0	0
T151	7238	4	0	0
T152	18711	64	0	0
T153	20393	85	0	0
T154	5688	4	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2885	0	0
T88	3468	4	0	0
T105	12601	77	0	0
T106	17232	2	0	0
T116	10463	13	0	0
T121	3456	51	0	0
T139	13977	44	0	0
T142	7888	14	0	0
T151	7238	12	0	0
T152	18711	86	0	0
T153	20393	50	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2643	0	0
T88	3468	16	0	0
T100	8110	3	0	0
T105	12601	42	0	0
T116	10463	81	0	0
T121	3456	28	0	0
T139	13977	46	0	0
T142	7888	41	0	0
T151	7238	24	0	0
T152	18711	57	0	0
T153	20393	84	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1210	0	0
T88	3468	4	0	0
T105	12601	7	0	0
T107	18759	4	0	0
T116	10463	20	0	0
T121	3456	7	0	0
T139	13977	34	0	0
T142	7888	23	0	0
T151	7238	22	0	0
T152	18711	49	0	0
T153	20393	117	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1272	0	0
T88	3468	9	0	0
T105	12601	22	0	0
T116	10463	24	0	0
T139	13977	28	0	0
T142	7888	11	0	0
T151	7238	2	0	0
T152	18711	57	0	0
T153	20393	36	0	0
T154	5688	14	0	0
T155	65262	81	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1380	0	0
T88	3468	8	0	0
T105	12601	22	0	0
T116	10463	28	0	0
T121	3456	8	0	0
T139	13977	31	0	0
T142	7888	15	0	0
T151	7238	23	0	0
T152	18711	83	0	0
T153	20393	76	0	0
T154	5688	17	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1298	0	0
T88	3468	11	0	0
T105	12601	9	0	0
T116	10463	21	0	0
T121	3456	7	0	0
T139	13977	33	0	0
T142	7888	61	0	0
T151	7238	19	0	0
T152	18711	51	0	0
T153	20393	40	0	0
T154	5688	17	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1750	0	0
T88	3468	8	0	0
T105	12601	25	0	0
T116	10463	26	0	0
T121	3456	5	0	0
T139	13977	49	0	0
T151	7238	26	0	0
T152	18711	96	0	0
T153	20393	51	0	0
T154	5688	32	0	0
T155	65262	108	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	2804	0	0
T15	7254	60	0	0
T19	0	28	0	0
T23	895	0	0	0
T24	4018	0	0	0
T25	162611	0	0	0
T26	116857	0	0	0
T27	80296	0	0	0
T28	27400	0	0	0
T34	273765	0	0	0
T35	0	24	0	0
T37	926	0	0	0
T38	50136	0	0	0
T156	0	13	0	0
T157	0	15	0	0
T158	0	10	0	0
T159	0	46	0	0
T160	0	7	0	0
T161	0	37	0	0
T162	0	50	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1352	0	0
T88	3468	8	0	0
T105	12601	23	0	0
T116	10463	23	0	0
T121	3456	4	0	0
T139	13977	37	0	0
T142	7888	34	0	0
T151	7238	16	0	0
T152	18711	68	0	0
T153	20393	62	0	0
T154	5688	9	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1257	0	0
T88	3468	4	0	0
T105	12601	11	0	0
T116	10463	21	0	0
T121	3456	9	0	0
T139	13977	20	0	0
T142	7888	4	0	0
T151	7238	11	0	0
T152	18711	52	0	0
T153	20393	57	0	0
T154	5688	6	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1118	0	0
T88	3468	3	0	0
T98	8474	3	0	0
T105	12601	19	0	0
T116	10463	12	0	0
T121	3456	7	0	0
T139	13977	17	0	0
T142	7888	36	0	0
T151	7238	1	0	0
T152	18711	36	0	0
T153	20393	110	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1102	0	0
T88	3468	12	0	0
T105	12601	7	0	0
T116	10463	16	0	0
T121	3456	1	0	0
T139	13977	23	0	0
T142	7888	2	0	0
T151	7238	32	0	0
T152	18711	54	0	0
T153	20393	92	0	0
T154	5688	4	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1071	0	0
T88	3468	3	0	0
T105	12601	10	0	0
T116	10463	32	0	0
T139	13977	18	0	0
T142	7888	33	0	0
T151	7238	24	0	0
T152	18711	56	0	0
T153	20393	29	0	0
T154	5688	6	0	0
T155	65262	24	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1155	0	0
T88	3468	2	0	0
T105	12601	5	0	0
T116	10463	30	0	0
T121	3456	3	0	0
T139	13977	60	0	0
T142	7888	49	0	0
T151	7238	19	0	0
T152	18711	90	0	0
T153	20393	67	0	0
T154	5688	4	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1531	0	0
T88	3468	5	0	0
T105	12601	21	0	0
T116	10463	27	0	0
T121	3456	4	0	0
T139	13977	37	0	0
T142	7888	18	0	0
T151	7238	24	0	0
T152	18711	38	0	0
T153	20393	78	0	0
T154	5688	23	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1067	0	0
T88	3468	8	0	0
T105	12601	16	0	0
T116	10463	20	0	0
T121	3456	2	0	0
T139	13977	19	0	0
T142	7888	5	0	0
T151	7238	37	0	0
T152	18711	40	0	0
T153	20393	46	0	0
T154	5688	7	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1616	0	0
T88	3468	17	0	0
T105	12601	22	0	0
T116	10463	26	0	0
T121	3456	1	0	0
T139	13977	23	0	0
T142	7888	36	0	0
T151	7238	37	0	0
T152	18711	48	0	0
T153	20393	36	0	0
T154	5688	6	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1420	0	0
T88	3468	8	0	0
T105	12601	19	0	0
T116	10463	29	0	0
T121	3456	7	0	0
T139	13977	64	0	0
T142	7888	26	0	0
T151	7238	18	0	0
T152	18711	111	0	0
T153	20393	56	0	0
T154	5688	10	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1182	0	0
T88	3468	6	0	0
T105	12601	7	0	0
T116	10463	12	0	0
T121	3456	3	0	0
T139	13977	57	0	0
T142	7888	24	0	0
T151	7238	30	0	0
T152	18711	31	0	0
T153	20393	87	0	0
T154	5688	4	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1162	0	0
T88	3468	6	0	0
T105	12601	2	0	0
T116	10463	25	0	0
T121	3456	4	0	0
T139	13977	44	0	0
T142	7888	16	0	0
T151	7238	13	0	0
T152	18711	66	0	0
T153	20393	81	0	0
T154	5688	9	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1182	0	0
T88	3468	8	0	0
T105	12601	2	0	0
T107	18759	7	0	0
T116	10463	28	0	0
T121	3456	2	0	0
T139	13977	39	0	0
T142	7888	27	0	0
T151	7238	8	0	0
T152	18711	59	0	0
T153	20393	57	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1183	0	0
T88	3468	2	0	0
T105	12601	17	0	0
T116	10463	15	0	0
T121	3456	5	0	0
T139	13977	43	0	0
T142	7888	41	0	0
T151	7238	4	0	0
T152	18711	32	0	0
T153	20393	63	0	0
T154	5688	4	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1101	0	0
T88	3468	16	0	0
T105	12601	12	0	0
T116	10463	23	0	0
T139	13977	21	0	0
T142	7888	10	0	0
T151	7238	6	0	0
T152	18711	30	0	0
T153	20393	87	0	0
T154	5688	15	0	0
T155	65262	53	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452460268	1248	0	0
T88	3468	4	0	0
T105	12601	15	0	0
T116	10463	12	0	0
T121	3456	3	0	0
T139	13977	71	0	0
T142	7888	11	0	0
T151	7238	30	0	0
T152	18711	62	0	0
T153	20393	84	0	0
T154	5688	5	0	0