Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3506920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4102015

1

T1

2935

T2

1771

T3

784

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4166540	1			T1	2361		T2	1802		T3	2037
values[0x0]	1720148	1			T1	1376		T2	438		T3	403
values[0x1]	1722247	1			T1	1431		T2	487		T3	362

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2483758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5125177

1

T1

3548

T2

1961

T3

1397

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30944	1			T1	18		T2	7		T3	10
valid_sources[0x01]	28335	1			T1	12		T2	13		T3	14
valid_sources[0x02]	26546	1			T1	26		T2	17		T3	7
valid_sources[0x03]	26598	1			T1	26		T2	11		T3	10
valid_sources[0x04]	27197	1			T1	21		T2	11		T3	8
valid_sources[0x05]	28610	1			T1	14		T2	6		T3	8
valid_sources[0x06]	27048	1			T1	17		T2	14		T3	13
valid_sources[0x07]	26796	1			T1	17		T2	11		T3	19
valid_sources[0x08]	26769	1			T1	21		T2	3		T3	17
valid_sources[0x09]	30826	1			T1	25		T2	13		T3	12
valid_sources[0x0a]	29633	1			T1	18		T2	7		T3	5
valid_sources[0x0b]	35692	1			T1	24		T2	8		T3	2
valid_sources[0x0c]	29946	1			T1	19		T2	13		T3	17
valid_sources[0x0d]	27606	1			T1	25		T2	14		T3	5
valid_sources[0x0e]	31947	1			T1	19		T2	8		T3	9
valid_sources[0x0f]	31483	1			T1	22		T2	11		T3	8
valid_sources[0x10]	32714	1			T1	22		T2	10		T3	13
valid_sources[0x11]	27637	1			T1	31		T2	6		T3	9
valid_sources[0x12]	28810	1			T1	16		T2	13		T3	16
valid_sources[0x13]	27430	1			T1	16		T2	14		T3	4
valid_sources[0x14]	31925	1			T1	11		T2	10		T3	16
valid_sources[0x15]	28685	1			T1	18		T2	9		T3	6
valid_sources[0x16]	30041	1			T1	16		T2	13		T3	13
valid_sources[0x17]	28858	1			T1	25		T2	7		T3	11
valid_sources[0x18]	29102	1			T1	19		T2	12		T3	13
valid_sources[0x19]	27905	1			T1	12		T2	18		T3	12
valid_sources[0x1a]	28828	1			T1	31		T2	6		T3	16
valid_sources[0x1b]	28558	1			T1	30		T2	19		T3	5
valid_sources[0x1c]	29052	1			T1	19		T2	5		T3	7
valid_sources[0x1d]	26710	1			T1	26		T2	8		T3	13
valid_sources[0x1e]	30219	1			T1	25		T2	5		T3	14
valid_sources[0x1f]	31565	1			T1	19		T2	14		T3	3
valid_sources[0x20]	28724	1			T1	34		T2	9		T3	16
valid_sources[0x21]	36384	1			T1	16		T2	8		T3	16
valid_sources[0x22]	31058	1			T1	28		T2	9		T3	16
valid_sources[0x23]	29053	1			T1	8		T2	13		T3	8
valid_sources[0x24]	27037	1			T1	18		T2	10		T3	16
valid_sources[0x25]	28938	1			T1	17		T2	11		T3	4
valid_sources[0x26]	27359	1			T1	30		T2	21		T3	25
valid_sources[0x27]	25448	1			T1	16		T2	6		T3	6
valid_sources[0x28]	31152	1			T1	28		T2	9		T3	14
valid_sources[0x29]	28034	1			T1	9		T2	16		T3	19
valid_sources[0x2a]	32441	1			T1	21		T2	10		T3	4
valid_sources[0x2b]	29788	1			T1	13		T2	11		T3	16
valid_sources[0x2c]	29960	1			T1	18		T2	20		T3	6
valid_sources[0x2d]	29599	1			T1	11		T2	10		T3	17
valid_sources[0x2e]	29760	1			T1	22		T2	11		T3	17
valid_sources[0x2f]	28363	1			T1	33		T2	10		T3	8
valid_sources[0x30]	30019	1			T1	16		T2	11		T3	15
valid_sources[0x31]	29179	1			T1	14		T2	10		T3	11
valid_sources[0x32]	26904	1			T1	30		T2	11		T3	7
valid_sources[0x33]	29051	1			T1	26		T2	10		T3	10
valid_sources[0x34]	31124	1			T1	17		T2	17		T3	4
valid_sources[0x35]	30175	1			T1	18		T2	12		T3	7
valid_sources[0x36]	36621	1			T1	27		T2	13		T3	15
valid_sources[0x37]	33074	1			T1	28		T2	11		T3	12
valid_sources[0x38]	29249	1			T1	19		T2	10		T3	12
valid_sources[0x39]	39059	1			T1	24		T2	11		T3	7
valid_sources[0x3a]	28552	1			T1	23		T2	19		T3	10
valid_sources[0x3b]	28216	1			T1	20		T2	13		T3	12
valid_sources[0x3c]	26828	1			T1	21		T2	14		T3	9
valid_sources[0x3d]	31342	1			T1	25		T2	9		T3	5
valid_sources[0x3e]	27793	1			T1	23		T2	10		T3	9
valid_sources[0x3f]	28481	1			T1	20		T2	7		T3	8
valid_sources[0x40]	30888	1			T1	15		T2	8		T3	20
valid_sources[0x41]	31691	1			T1	23		T2	6		T3	6
valid_sources[0x42]	27856	1			T1	20		T2	11		T3	13
valid_sources[0x43]	30760	1			T1	13		T2	15		T3	5
valid_sources[0x44]	30668	1			T1	14		T2	9		T3	12
valid_sources[0x45]	30987	1			T1	17		T2	10		T3	10
valid_sources[0x46]	31108	1			T1	19		T2	8		T3	12
valid_sources[0x47]	28327	1			T1	16		T2	8		T3	12
valid_sources[0x48]	28050	1			T1	17		T2	9		T3	12
valid_sources[0x49]	29580	1			T1	24		T2	17		T3	21
valid_sources[0x4a]	27326	1			T1	25		T2	14		T3	10
valid_sources[0x4b]	33524	1			T1	22		T2	12		T3	8
valid_sources[0x4c]	27887	1			T1	29		T2	11		T3	11
valid_sources[0x4d]	26778	1			T1	27		T2	12		T3	15
valid_sources[0x4e]	28549	1			T1	23		T2	8		T3	12
valid_sources[0x4f]	28291	1			T1	24		T2	10		T3	13
valid_sources[0x50]	27751	1			T1	29		T2	6		T3	10
valid_sources[0x51]	31196	1			T1	29		T2	18		T3	7
valid_sources[0x52]	28407	1			T1	14		T2	8		T3	6
valid_sources[0x53]	30314	1			T1	22		T2	5		T3	7
valid_sources[0x54]	30582	1			T1	22		T2	9		T3	2
valid_sources[0x55]	34664	1			T1	21		T2	11		T3	15
valid_sources[0x56]	34795	1			T1	22		T2	14		T3	17
valid_sources[0x57]	29920	1			T1	22		T2	5		T3	11
valid_sources[0x58]	29932	1			T1	18		T2	14		T3	6
valid_sources[0x59]	33497	1			T1	31		T2	16		T3	9
valid_sources[0x5a]	27897	1			T1	21		T2	8		T3	14
valid_sources[0x5b]	27668	1			T1	24		T2	12		T3	5
valid_sources[0x5c]	30491	1			T1	22		T2	8		T3	12
valid_sources[0x5d]	27291	1			T1	23		T2	11		T3	14
valid_sources[0x5e]	25389	1			T1	19		T2	10		T3	15
valid_sources[0x5f]	31051	1			T1	21		T2	13		T3	10
valid_sources[0x60]	41010	1			T1	18		T2	14		T3	7
valid_sources[0x61]	28755	1			T1	28		T2	17		T3	8
valid_sources[0x62]	31833	1			T1	18		T2	12		T3	6
valid_sources[0x63]	26771	1			T1	26		T2	9		T3	9
valid_sources[0x64]	31239	1			T1	18		T2	9		T3	18
valid_sources[0x65]	27138	1			T1	18		T2	8		T3	9
valid_sources[0x66]	31793	1			T1	16		T2	13		T3	7
valid_sources[0x67]	28616	1			T1	21		T2	5		T3	12
valid_sources[0x68]	29126	1			T1	13		T2	12		T3	13
valid_sources[0x69]	27022	1			T1	23		T2	11		T3	6
valid_sources[0x6a]	26840	1			T1	12		T2	12		T3	2
valid_sources[0x6b]	29544	1			T1	18		T2	6		T3	6
valid_sources[0x6c]	26970	1			T1	20		T2	8		T3	21
valid_sources[0x6d]	33882	1			T1	18		T2	12		T3	11
valid_sources[0x6e]	27939	1			T1	21		T2	5		T3	21
valid_sources[0x6f]	28088	1			T1	18		T2	13		T3	8
valid_sources[0x70]	27119	1			T1	21		T2	16		T3	10
valid_sources[0x71]	28859	1			T1	30		T2	8		T3	4
valid_sources[0x72]	26516	1			T1	15		T2	11		T3	10
valid_sources[0x73]	30540	1			T1	12		T2	16		T3	10
valid_sources[0x74]	27911	1			T1	12		T2	11		T3	9
valid_sources[0x75]	27163	1			T1	22		T2	7		T3	6
valid_sources[0x76]	39753	1			T1	11		T2	9		T3	10
valid_sources[0x77]	27771	1			T1	30		T2	8		T3	5
valid_sources[0x78]	27782	1			T1	11		T2	16		T3	14
valid_sources[0x79]	30710	1			T1	19		T2	11		T3	7
valid_sources[0x7a]	28528	1			T1	18		T2	8		T3	4
valid_sources[0x7b]	34630	1			T1	19		T2	13		T3	3
valid_sources[0x7c]	28677	1			T1	16		T2	10		T3	12
valid_sources[0x7d]	27337	1			T1	17		T2	9		T3	19
valid_sources[0x7e]	26310	1			T1	14		T2	9		T3	13
valid_sources[0x7f]	29531	1			T1	20		T2	7		T3	7
valid_sources[0x80]	27826	1			T1	22		T2	14		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

986874

1

T1

820

T2

858

T3

195

values[0x0]

all_enables

biggest_size

1569036

1

T1

1060

T2

438

T3

319

values[0x1]

all_enables

biggest_size

1546105

1

T1

1055

T2

475

T3

270