Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3528038

1

T1

2233

T2

956

T3

2018

full_word

4101073

1

T1

2935

T2

1771

T3

784

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7628731	1			T1	5168		T2	2727		T3	2802
auto[TlIntgErrCmd]	133	1			T101	2		T104	6		T105	5
auto[TlIntgErrData]	139	1			T101	5		T104	8		T105	2
auto[TlIntgErrBoth]	108	1			T101	3		T104	6		T105	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4167807

1

T1

2361

T2

1802

T3

2037

auto[1]

3461304

1

T1

2807

T2

925

T3

765

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3180683	1			T1	1541		T2	944		T3	1842
auto[TlIntgErrNone]	partial	auto[1]	347010	1			T1	692		T2	12		T3	176
auto[TlIntgErrNone]	full_word	auto[0]	986954	1			T1	820		T2	858		T3	195
auto[TlIntgErrNone]	full_word	auto[1]	3114084	1			T1	2115		T2	913		T3	589
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T104	4		T105	1		T186	3
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T101	2		T104	1		T105	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T186	1		T190	1		T162	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T104	1		T186	2		T191	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T101	2		T104	4		T186	1
auto[TlIntgErrData]	partial	auto[1]	63	1			T101	3		T104	3		T105	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T192	1		T162	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T104	1		T186	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T101	2		T104	3		T105	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T101	1		T104	1		T105	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T104	1		T189	1		T193	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T104	1		T193	1		T194	1