Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428374673	2774838	0	0
DepthKnown_A	428374673	428241788	0	0
RvalidKnown_A	428374673	428241788	0	0
WreadyKnown_A	428374673	428241788	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	2774838	0	0
T2	47266	1663	0	0
T3	179614	0	0	0
T4	8397	1663	0	0
T5	85941	4989	0	0
T6	1057	0	0	0
T7	92780	1665	0	0
T8	15893	0	0	0
T9	1643	0	0	0
T10	107929	0	0	0
T11	157396	832	0	0
T12	0	1663	0	0
T13	0	5822	0	0
T14	0	1663	0	0
T15	0	4159	0	0
T39	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428374673	2932510	0	0
DepthKnown_A	428374673	428241788	0	0
RvalidKnown_A	428374673	428241788	0	0
WreadyKnown_A	428374673	428241788	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	2932510	0	0
T2	47266	832	0	0
T3	179614	0	0	0
T4	8397	832	0	0
T5	85941	2496	0	0
T6	1057	0	0	0
T7	92780	834	0	0
T8	15893	0	0	0
T9	1643	0	0	0
T10	107929	0	0	0
T11	157396	832	0	0
T12	0	832	0	0
T13	0	4160	0	0
T14	0	832	0	0
T15	0	3328	0	0
T39	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428374673	183029	0	0
DepthKnown_A	428374673	428241788	0	0
RvalidKnown_A	428374673	428241788	0	0
WreadyKnown_A	428374673	428241788	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	183029	0	0
T1	133057	657	0	0
T2	47266	0	0	0
T3	179614	152	0	0
T4	8397	0	0	0
T5	85941	193	0	0
T6	1057	0	0	0
T7	92780	0	0	0
T8	15893	24	0	0
T9	1643	0	0	0
T10	107929	146	0	0
T13	0	467	0	0
T15	0	2122	0	0
T16	0	128	0	0
T28	0	60	0	0
T39	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428374673	383455	0	0
DepthKnown_A	428374673	428241788	0	0
RvalidKnown_A	428374673	428241788	0	0
WreadyKnown_A	428374673	428241788	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	383455	0	0
T1	133057	2911	0	0
T2	47266	0	0	0
T3	179614	705	0	0
T4	8397	0	0	0
T5	85941	193	0	0
T6	1057	0	0	0
T7	92780	0	0	0
T8	15893	97	0	0
T9	1643	0	0	0
T10	107929	603	0	0
T13	0	467	0	0
T15	0	2122	0	0
T16	0	128	0	0
T28	0	60	0	0
T39	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428374673	5997634	0	0
DepthKnown_A	428374673	428241788	0	0
RvalidKnown_A	428374673	428241788	0	0
WreadyKnown_A	428374673	428241788	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	5997634	0	0
T1	133057	4945	0	0
T2	47266	1895	0	0
T3	179614	2698	0	0
T4	8397	54	0	0
T5	85941	450	0	0
T6	1057	21	0	0
T7	92780	74	0	0
T8	15893	807	0	0
T9	1643	67	0	0
T10	107929	1872	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428374673	11655023	0	0
DepthKnown_A	428374673	428241788	0	0
RvalidKnown_A	428374673	428241788	0	0
WreadyKnown_A	428374673	428241788	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	11655023	0	0
T1	133057	20223	0	0
T2	47266	1895	0	0
T3	179614	11771	0	0
T4	8397	53	0	0
T5	85941	448	0	0
T6	1057	21	0	0
T7	92780	310	0	0
T8	15893	3672	0	0
T9	1643	67	0	0
T10	107929	8091	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428374673	428241788	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0