Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T15
1	0	Covered	T5,T13,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T5,T13,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	711614035	567398139	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	711614035	3601955	0	0
GntImpliesValid_A	711614035	3601955	0	0
GrantKnown_A	711614035	567398139	0	0
IdxKnown_A	711614035	567398139	0	0
IndexIsCorrect_A	711614035	3601955	0	0
LockArbDecision_A	711614035	0	0	0
NoReadyValidNoGrant_A	711614035	0	0	0
ReadyAndValidImplyGrant_A	711614035	3601955	0	0
ReqAndReadyImplyGrant_A	711614035	3601955	0	0
ReqImpliesValid_A	711614035	3601955	0	0
ReqStaysHighUntilGranted0_M	711614035	0	0	0
RoundRobin_A	711614035	5	0	976
ValidKnown_A	711614035	567398139	0	0
gen_data_port_assertion.DataFlow_A	711614035	3601955	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	567398139	0	0
T1	447264	442654	0	0
T2	132424	89460	0	0
T3	226324	201198	0	0
T4	29363	18485	0	0
T5	632655	358491	0	0
T6	1057	979	0	0
T7	268270	180105	0	0
T8	19861	17791	0	0
T9	1643	1565	0	0
T10	149971	128424	0	0
T11	50062	25031	0	0
T12	13856	6928	0	0
T13	265388	262978	0	0
T14	0	4919	0	0
T15	0	682390	0	0
T16	0	203766	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	3601955	0	0
T1	447264	5996	0	0
T2	89845	832	0	0
T3	202969	1519	0	0
T4	18880	832	0	0
T5	632655	6414	0	0
T6	1057	0	0	0
T7	268270	832	0	0
T8	19861	167	0	0
T9	1643	0	0	0
T10	149971	1177	0	0
T11	50062	832	0	0
T12	13856	832	0	0
T13	265388	2821	0	0
T14	4919	0	0	0
T15	699229	13900	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	3384	262	0	0
T42	0	4448	0	0
T45	0	1569	0	0
T51	0	7	0	0
T52	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	3601955	0	0
T1	447264	5996	0	0
T2	89845	832	0	0
T3	202969	1519	0	0
T4	18880	832	0	0
T5	632655	6414	0	0
T6	1057	0	0	0
T7	268270	832	0	0
T8	19861	167	0	0
T9	1643	0	0	0
T10	149971	1177	0	0
T11	50062	832	0	0
T12	13856	832	0	0
T13	265388	2821	0	0
T14	4919	0	0	0
T15	699229	13900	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	3384	262	0	0
T42	0	4448	0	0
T45	0	1569	0	0
T51	0	7	0	0
T52	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	567398139	0	0
T1	447264	442654	0	0
T2	132424	89460	0	0
T3	226324	201198	0	0
T4	29363	18485	0	0
T5	632655	358491	0	0
T6	1057	979	0	0
T7	268270	180105	0	0
T8	19861	17791	0	0
T9	1643	1565	0	0
T10	149971	128424	0	0
T11	50062	25031	0	0
T12	13856	6928	0	0
T13	265388	262978	0	0
T14	0	4919	0	0
T15	0	682390	0	0
T16	0	203766	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	567398139	0	0
T1	447264	442654	0	0
T2	132424	89460	0	0
T3	226324	201198	0	0
T4	29363	18485	0	0
T5	632655	358491	0	0
T6	1057	979	0	0
T7	268270	180105	0	0
T8	19861	17791	0	0
T9	1643	1565	0	0
T10	149971	128424	0	0
T11	50062	25031	0	0
T12	13856	6928	0	0
T13	265388	262978	0	0
T14	0	4919	0	0
T15	0	682390	0	0
T16	0	203766	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	3601955	0	0
T1	447264	5996	0	0
T2	89845	832	0	0
T3	202969	1519	0	0
T4	18880	832	0	0
T5	632655	6414	0	0
T6	1057	0	0	0
T7	268270	832	0	0
T8	19861	167	0	0
T9	1643	0	0	0
T10	149971	1177	0	0
T11	50062	832	0	0
T12	13856	832	0	0
T13	265388	2821	0	0
T14	4919	0	0	0
T15	699229	13900	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	3384	262	0	0
T42	0	4448	0	0
T45	0	1569	0	0
T51	0	7	0	0
T52	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	3601955	0	0
T1	447264	5996	0	0
T2	89845	832	0	0
T3	202969	1519	0	0
T4	18880	832	0	0
T5	632655	6414	0	0
T6	1057	0	0	0
T7	268270	832	0	0
T8	19861	167	0	0
T9	1643	0	0	0
T10	149971	1177	0	0
T11	50062	832	0	0
T12	13856	832	0	0
T13	265388	2821	0	0
T14	4919	0	0	0
T15	699229	13900	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	3384	262	0	0
T42	0	4448	0	0
T45	0	1569	0	0
T51	0	7	0	0
T52	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	3601955	0	0
T1	447264	5996	0	0
T2	89845	832	0	0
T3	202969	1519	0	0
T4	18880	832	0	0
T5	632655	6414	0	0
T6	1057	0	0	0
T7	268270	832	0	0
T8	19861	167	0	0
T9	1643	0	0	0
T10	149971	1177	0	0
T11	50062	832	0	0
T12	13856	832	0	0
T13	265388	2821	0	0
T14	4919	0	0	0
T15	699229	13900	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	3384	262	0	0
T42	0	4448	0	0
T45	0	1569	0	0
T51	0	7	0	0
T52	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	3601955	0	0
T1	447264	5996	0	0
T2	89845	832	0	0
T3	202969	1519	0	0
T4	18880	832	0	0
T5	632655	6414	0	0
T6	1057	0	0	0
T7	268270	832	0	0
T8	19861	167	0	0
T9	1643	0	0	0
T10	149971	1177	0	0
T11	50062	832	0	0
T12	13856	832	0	0
T13	265388	2821	0	0
T14	4919	0	0	0
T15	699229	13900	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	3384	262	0	0
T42	0	4448	0	0
T45	0	1569	0	0
T51	0	7	0	0
T52	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	5	0	976
T18	4196	0	0	1
T41	3192	0	0	1
T49	617187	0	0	1
T53	325955	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	393028	0	0	1
T59	8977	0	0	1
T60	3925	0	0	1
T61	44509	0	0	1
T62	7822	0	0	1
T63	131935	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	567398139	0	0
T1	447264	442654	0	0
T2	132424	89460	0	0
T3	226324	201198	0	0
T4	29363	18485	0	0
T5	632655	358491	0	0
T6	1057	979	0	0
T7	268270	180105	0	0
T8	19861	17791	0	0
T9	1643	1565	0	0
T10	149971	128424	0	0
T11	50062	25031	0	0
T12	13856	6928	0	0
T13	265388	262978	0	0
T14	0	4919	0	0
T15	0	682390	0	0
T16	0	203766	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711614035	3601955	0	0
T1	447264	5996	0	0
T2	89845	832	0	0
T3	202969	1519	0	0
T4	18880	832	0	0
T5	632655	6414	0	0
T6	1057	0	0	0
T7	268270	832	0	0
T8	19861	167	0	0
T9	1643	0	0	0
T10	149971	1177	0	0
T11	50062	832	0	0
T12	13856	832	0	0
T13	265388	2821	0	0
T14	4919	0	0	0
T15	699229	13900	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	3384	262	0	0
T42	0	4448	0	0
T45	0	1569	0	0
T51	0	7	0	0
T52	0	9	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	142844775	27603646	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	142844775	607739	0	0
GntImpliesValid_A	142844775	607739	0	0
GrantKnown_A	142844775	27603646	0	0
IdxKnown_A	142844775	27603646	0	0
IndexIsCorrect_A	142844775	607739	0	0
LockArbDecision_A	142844775	0	0	0
NoReadyValidNoGrant_A	142844775	0	0	0
ReadyAndValidImplyGrant_A	142844775	607739	0	0
ReqAndReadyImplyGrant_A	142844775	607739	0	0
ReqImpliesValid_A	142844775	607739	0	0
ReqStaysHighUntilGranted0_M	142844775	0	0	0
RoundRobin_A	142844775	0	0	0
ValidKnown_A	142844775	27603646	0	0
gen_data_port_assertion.DataFlow_A	142844775	607739	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	27603646	0	0
T1	314207	309664	0	0
T2	42579	0	0	0
T3	23355	21648	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	1984	0	0
T10	21021	20592	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	53104	0	0
T15	0	392824	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	607739	0	0
T1	314207	4010	0	0
T2	42579	0	0	0
T3	23355	996	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	118	0	0
T10	21021	800	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	2040	0	0
T15	0	11544	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	0	262	0	0
T42	0	764	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	607739	0	0
T1	314207	4010	0	0
T2	42579	0	0	0
T3	23355	996	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	118	0	0
T10	21021	800	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	2040	0	0
T15	0	11544	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	0	262	0	0
T42	0	764	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	27603646	0	0
T1	314207	309664	0	0
T2	42579	0	0	0
T3	23355	21648	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	1984	0	0
T10	21021	20592	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	53104	0	0
T15	0	392824	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	27603646	0	0
T1	314207	309664	0	0
T2	42579	0	0	0
T3	23355	21648	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	1984	0	0
T10	21021	20592	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	53104	0	0
T15	0	392824	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	607739	0	0
T1	314207	4010	0	0
T2	42579	0	0	0
T3	23355	996	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	118	0	0
T10	21021	800	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	2040	0	0
T15	0	11544	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	0	262	0	0
T42	0	764	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	607739	0	0
T1	314207	4010	0	0
T2	42579	0	0	0
T3	23355	996	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	118	0	0
T10	21021	800	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	2040	0	0
T15	0	11544	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	0	262	0	0
T42	0	764	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	607739	0	0
T1	314207	4010	0	0
T2	42579	0	0	0
T3	23355	996	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	118	0	0
T10	21021	800	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	2040	0	0
T15	0	11544	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	0	262	0	0
T42	0	764	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	607739	0	0
T1	314207	4010	0	0
T2	42579	0	0	0
T3	23355	996	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	118	0	0
T10	21021	800	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	2040	0	0
T15	0	11544	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	0	262	0	0
T42	0	764	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	27603646	0	0
T1	314207	309664	0	0
T2	42579	0	0	0
T3	23355	21648	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	1984	0	0
T10	21021	20592	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	53104	0	0
T15	0	392824	0	0
T23	0	1728	0	0
T25	0	109016	0	0
T27	0	40904	0	0
T28	0	3384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	607739	0	0
T1	314207	4010	0	0
T2	42579	0	0	0
T3	23355	996	0	0
T4	10483	0	0	0
T5	273357	0	0	0
T7	87745	0	0	0
T8	1984	118	0	0
T10	21021	800	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	0	2040	0	0
T15	0	11544	0	0
T23	0	85	0	0
T27	0	1661	0	0
T28	0	262	0	0
T42	0	764	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T15
1	0	Covered	T5,T13,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T5,T13,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T13,T15
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	142844775	113959051	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	142844775	812423	0	0
GntImpliesValid_A	142844775	812423	0	0
GrantKnown_A	142844775	113959051	0	0
IdxKnown_A	142844775	113959051	0	0
IndexIsCorrect_A	142844775	812423	0	0
LockArbDecision_A	142844775	0	0	0
NoReadyValidNoGrant_A	142844775	0	0	0
ReadyAndValidImplyGrant_A	142844775	812423	0	0
ReqAndReadyImplyGrant_A	142844775	812423	0	0
ReqImpliesValid_A	142844775	812423	0	0
ReqStaysHighUntilGranted0_M	142844775	0	0	0
RoundRobin_A	142844775	0	0	0
ValidKnown_A	142844775	113959051	0	0
gen_data_port_assertion.DataFlow_A	142844775	812423	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	113959051	0	0
T2	42579	42272	0	0
T3	23355	0	0	0
T4	10483	10152	0	0
T5	273357	272640	0	0
T7	87745	87404	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	25031	0	0
T12	6928	6928	0	0
T13	265388	209874	0	0
T14	0	4919	0	0
T15	0	289566	0	0
T16	0	203766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	812423	0	0
T5	273357	3716	0	0
T7	87745	0	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	265388	781	0	0
T14	4919	0	0	0
T15	699229	2356	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T28	3384	0	0	0
T42	0	3684	0	0
T45	0	1569	0	0
T46	0	3214	0	0
T51	0	7	0	0
T52	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	812423	0	0
T5	273357	3716	0	0
T7	87745	0	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	265388	781	0	0
T14	4919	0	0	0
T15	699229	2356	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T28	3384	0	0	0
T42	0	3684	0	0
T45	0	1569	0	0
T46	0	3214	0	0
T51	0	7	0	0
T52	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	113959051	0	0
T2	42579	42272	0	0
T3	23355	0	0	0
T4	10483	10152	0	0
T5	273357	272640	0	0
T7	87745	87404	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	25031	0	0
T12	6928	6928	0	0
T13	265388	209874	0	0
T14	0	4919	0	0
T15	0	289566	0	0
T16	0	203766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	113959051	0	0
T2	42579	42272	0	0
T3	23355	0	0	0
T4	10483	10152	0	0
T5	273357	272640	0	0
T7	87745	87404	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	25031	0	0
T12	6928	6928	0	0
T13	265388	209874	0	0
T14	0	4919	0	0
T15	0	289566	0	0
T16	0	203766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	812423	0	0
T5	273357	3716	0	0
T7	87745	0	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	265388	781	0	0
T14	4919	0	0	0
T15	699229	2356	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T28	3384	0	0	0
T42	0	3684	0	0
T45	0	1569	0	0
T46	0	3214	0	0
T51	0	7	0	0
T52	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	812423	0	0
T5	273357	3716	0	0
T7	87745	0	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	265388	781	0	0
T14	4919	0	0	0
T15	699229	2356	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T28	3384	0	0	0
T42	0	3684	0	0
T45	0	1569	0	0
T46	0	3214	0	0
T51	0	7	0	0
T52	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	812423	0	0
T5	273357	3716	0	0
T7	87745	0	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	265388	781	0	0
T14	4919	0	0	0
T15	699229	2356	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T28	3384	0	0	0
T42	0	3684	0	0
T45	0	1569	0	0
T46	0	3214	0	0
T51	0	7	0	0
T52	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	812423	0	0
T5	273357	3716	0	0
T7	87745	0	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	265388	781	0	0
T14	4919	0	0	0
T15	699229	2356	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T28	3384	0	0	0
T42	0	3684	0	0
T45	0	1569	0	0
T46	0	3214	0	0
T51	0	7	0	0
T52	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	113959051	0	0
T2	42579	42272	0	0
T3	23355	0	0	0
T4	10483	10152	0	0
T5	273357	272640	0	0
T7	87745	87404	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	25031	0	0
T12	6928	6928	0	0
T13	265388	209874	0	0
T14	0	4919	0	0
T15	0	289566	0	0
T16	0	203766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142844775	812423	0	0
T5	273357	3716	0	0
T7	87745	0	0	0
T8	1984	0	0	0
T10	21021	0	0	0
T11	25031	0	0	0
T12	6928	0	0	0
T13	265388	781	0	0
T14	4919	0	0	0
T15	699229	2356	0	0
T16	0	4512	0	0
T17	0	10794	0	0
T28	3384	0	0	0
T42	0	3684	0	0
T45	0	1569	0	0
T46	0	3214	0	0
T51	0	7	0	0
T52	0	9	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425924485	425835442	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	425924485	2181793	0	0
GntImpliesValid_A	425924485	2181793	0	0
GrantKnown_A	425924485	425835442	0	0
IdxKnown_A	425924485	425835442	0	0
IndexIsCorrect_A	425924485	2181793	0	0
LockArbDecision_A	425924485	0	0	0
NoReadyValidNoGrant_A	425924485	0	0	0
ReadyAndValidImplyGrant_A	425924485	2181793	0	0
ReqAndReadyImplyGrant_A	425924485	2181793	0	0
ReqImpliesValid_A	425924485	2181793	0	0
ReqStaysHighUntilGranted0_M	425924485	0	0	0
RoundRobin_A	425924485	5	0	976
ValidKnown_A	425924485	425835442	0	0
gen_data_port_assertion.DataFlow_A	425924485	2181793	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	425835442	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	2181793	0	0
T1	133057	1986	0	0
T2	47266	832	0	0
T3	179614	523	0	0
T4	8397	832	0	0
T5	85941	2698	0	0
T6	1057	0	0	0
T7	92780	832	0	0
T8	15893	49	0	0
T9	1643	0	0	0
T10	107929	377	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	2181793	0	0
T1	133057	1986	0	0
T2	47266	832	0	0
T3	179614	523	0	0
T4	8397	832	0	0
T5	85941	2698	0	0
T6	1057	0	0	0
T7	92780	832	0	0
T8	15893	49	0	0
T9	1643	0	0	0
T10	107929	377	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	425835442	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	425835442	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	2181793	0	0
T1	133057	1986	0	0
T2	47266	832	0	0
T3	179614	523	0	0
T4	8397	832	0	0
T5	85941	2698	0	0
T6	1057	0	0	0
T7	92780	832	0	0
T8	15893	49	0	0
T9	1643	0	0	0
T10	107929	377	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	2181793	0	0
T1	133057	1986	0	0
T2	47266	832	0	0
T3	179614	523	0	0
T4	8397	832	0	0
T5	85941	2698	0	0
T6	1057	0	0	0
T7	92780	832	0	0
T8	15893	49	0	0
T9	1643	0	0	0
T10	107929	377	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	2181793	0	0
T1	133057	1986	0	0
T2	47266	832	0	0
T3	179614	523	0	0
T4	8397	832	0	0
T5	85941	2698	0	0
T6	1057	0	0	0
T7	92780	832	0	0
T8	15893	49	0	0
T9	1643	0	0	0
T10	107929	377	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	2181793	0	0
T1	133057	1986	0	0
T2	47266	832	0	0
T3	179614	523	0	0
T4	8397	832	0	0
T5	85941	2698	0	0
T6	1057	0	0	0
T7	92780	832	0	0
T8	15893	49	0	0
T9	1643	0	0	0
T10	107929	377	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	5	0	976
T18	4196	0	0	1
T41	3192	0	0	1
T49	617187	0	0	1
T53	325955	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	393028	0	0	1
T59	8977	0	0	1
T60	3925	0	0	1
T61	44509	0	0	1
T62	7822	0	0	1
T63	131935	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	425835442	0	0
T1	133057	132990	0	0
T2	47266	47188	0	0
T3	179614	179550	0	0
T4	8397	8333	0	0
T5	85941	85851	0	0
T6	1057	979	0	0
T7	92780	92701	0	0
T8	15893	15807	0	0
T9	1643	1565	0	0
T10	107929	107832	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425924485	2181793	0	0
T1	133057	1986	0	0
T2	47266	832	0	0
T3	179614	523	0	0
T4	8397	832	0	0
T5	85941	2698	0	0
T6	1057	0	0	0
T7	92780	832	0	0
T8	15893	49	0	0
T9	1643	0	0	0
T10	107929	377	0	0
T11	0	832	0	0
T12	0	832	0	0