Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
3579 |
0 |
0 |
T99 |
19521 |
197 |
0 |
0 |
T100 |
5469 |
14 |
0 |
0 |
T101 |
10388 |
2 |
0 |
0 |
T102 |
15806 |
213 |
0 |
0 |
T103 |
20002 |
340 |
0 |
0 |
T104 |
64799 |
2 |
0 |
0 |
T106 |
4983 |
8 |
0 |
0 |
T112 |
10906 |
36 |
0 |
0 |
T117 |
8065 |
4 |
0 |
0 |
T118 |
12451 |
7 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2241 |
0 |
0 |
T104 |
64799 |
82 |
0 |
0 |
T121 |
9002 |
3 |
0 |
0 |
T124 |
7076 |
17 |
0 |
0 |
T127 |
10178 |
11 |
0 |
0 |
T131 |
4040 |
7 |
0 |
0 |
T146 |
6969 |
6 |
0 |
0 |
T158 |
9535 |
10 |
0 |
0 |
T159 |
8510 |
22 |
0 |
0 |
T160 |
180040 |
440 |
0 |
0 |
T161 |
14463 |
8 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2171 |
0 |
0 |
T104 |
64799 |
88 |
0 |
0 |
T121 |
9002 |
1 |
0 |
0 |
T124 |
7076 |
6 |
0 |
0 |
T127 |
10178 |
10 |
0 |
0 |
T131 |
4040 |
8 |
0 |
0 |
T146 |
6969 |
37 |
0 |
0 |
T158 |
9535 |
2 |
0 |
0 |
T159 |
8510 |
5 |
0 |
0 |
T160 |
180040 |
413 |
0 |
0 |
T161 |
14463 |
11 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2665 |
0 |
0 |
T104 |
64799 |
145 |
0 |
0 |
T121 |
9002 |
27 |
0 |
0 |
T124 |
7076 |
6 |
0 |
0 |
T127 |
10178 |
2 |
0 |
0 |
T146 |
6969 |
47 |
0 |
0 |
T158 |
9535 |
17 |
0 |
0 |
T159 |
8510 |
16 |
0 |
0 |
T160 |
180040 |
434 |
0 |
0 |
T161 |
14463 |
9 |
0 |
0 |
T162 |
36718 |
49 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
10098 |
0 |
0 |
T104 |
64799 |
1651 |
0 |
0 |
T121 |
9002 |
237 |
0 |
0 |
T124 |
7076 |
98 |
0 |
0 |
T127 |
10178 |
189 |
0 |
0 |
T131 |
4040 |
139 |
0 |
0 |
T146 |
6969 |
11 |
0 |
0 |
T158 |
9535 |
134 |
0 |
0 |
T159 |
8510 |
148 |
0 |
0 |
T160 |
180040 |
422 |
0 |
0 |
T161 |
14463 |
86 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
8427 |
0 |
0 |
T104 |
64799 |
1217 |
0 |
0 |
T121 |
9002 |
6 |
0 |
0 |
T124 |
7076 |
135 |
0 |
0 |
T127 |
10178 |
54 |
0 |
0 |
T131 |
4040 |
4 |
0 |
0 |
T146 |
6969 |
21 |
0 |
0 |
T158 |
9535 |
132 |
0 |
0 |
T159 |
8510 |
15 |
0 |
0 |
T160 |
180040 |
412 |
0 |
0 |
T161 |
14463 |
146 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
7723 |
0 |
0 |
T104 |
64799 |
1004 |
0 |
0 |
T121 |
9002 |
111 |
0 |
0 |
T127 |
10178 |
45 |
0 |
0 |
T131 |
4040 |
3 |
0 |
0 |
T146 |
6969 |
21 |
0 |
0 |
T158 |
9535 |
57 |
0 |
0 |
T159 |
8510 |
32 |
0 |
0 |
T160 |
180040 |
444 |
0 |
0 |
T161 |
14463 |
89 |
0 |
0 |
T162 |
36718 |
531 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
8922 |
0 |
0 |
T99 |
19521 |
5 |
0 |
0 |
T104 |
64799 |
915 |
0 |
0 |
T121 |
9002 |
111 |
0 |
0 |
T124 |
7076 |
109 |
0 |
0 |
T127 |
10178 |
135 |
0 |
0 |
T131 |
4040 |
136 |
0 |
0 |
T146 |
6969 |
6 |
0 |
0 |
T158 |
9535 |
66 |
0 |
0 |
T159 |
8510 |
66 |
0 |
0 |
T160 |
180040 |
458 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
8745 |
0 |
0 |
T104 |
64799 |
904 |
0 |
0 |
T121 |
9002 |
250 |
0 |
0 |
T124 |
7076 |
200 |
0 |
0 |
T127 |
10178 |
190 |
0 |
0 |
T131 |
4040 |
145 |
0 |
0 |
T146 |
6969 |
14 |
0 |
0 |
T158 |
9535 |
12 |
0 |
0 |
T159 |
8510 |
70 |
0 |
0 |
T160 |
180040 |
493 |
0 |
0 |
T161 |
14463 |
141 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
8961 |
0 |
0 |
T104 |
64799 |
1061 |
0 |
0 |
T121 |
9002 |
245 |
0 |
0 |
T124 |
7076 |
136 |
0 |
0 |
T127 |
10178 |
114 |
0 |
0 |
T131 |
4040 |
128 |
0 |
0 |
T146 |
6969 |
13 |
0 |
0 |
T158 |
9535 |
102 |
0 |
0 |
T159 |
8510 |
68 |
0 |
0 |
T160 |
180040 |
484 |
0 |
0 |
T161 |
14463 |
90 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
9445 |
0 |
0 |
T104 |
64799 |
1658 |
0 |
0 |
T121 |
9002 |
291 |
0 |
0 |
T124 |
7076 |
129 |
0 |
0 |
T127 |
10178 |
133 |
0 |
0 |
T131 |
4040 |
3 |
0 |
0 |
T158 |
9535 |
71 |
0 |
0 |
T159 |
8510 |
8 |
0 |
0 |
T160 |
180040 |
460 |
0 |
0 |
T161 |
14463 |
61 |
0 |
0 |
T162 |
36718 |
747 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
8687 |
0 |
0 |
T104 |
64799 |
1069 |
0 |
0 |
T121 |
9002 |
251 |
0 |
0 |
T124 |
7076 |
1 |
0 |
0 |
T127 |
10178 |
102 |
0 |
0 |
T131 |
4040 |
4 |
0 |
0 |
T158 |
9535 |
96 |
0 |
0 |
T159 |
8510 |
75 |
0 |
0 |
T160 |
180040 |
397 |
0 |
0 |
T161 |
14463 |
111 |
0 |
0 |
T162 |
36718 |
644 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4860 |
0 |
0 |
T104 |
64799 |
568 |
0 |
0 |
T121 |
9002 |
3 |
0 |
0 |
T124 |
7076 |
9 |
0 |
0 |
T127 |
10178 |
28 |
0 |
0 |
T131 |
4040 |
6 |
0 |
0 |
T146 |
6969 |
19 |
0 |
0 |
T158 |
9535 |
36 |
0 |
0 |
T159 |
8510 |
2 |
0 |
0 |
T160 |
180040 |
415 |
0 |
0 |
T161 |
14463 |
33 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4586 |
0 |
0 |
T104 |
64799 |
616 |
0 |
0 |
T121 |
9002 |
82 |
0 |
0 |
T124 |
7076 |
31 |
0 |
0 |
T127 |
10178 |
58 |
0 |
0 |
T131 |
4040 |
1 |
0 |
0 |
T146 |
6969 |
42 |
0 |
0 |
T158 |
9535 |
58 |
0 |
0 |
T159 |
8510 |
12 |
0 |
0 |
T160 |
180040 |
437 |
0 |
0 |
T161 |
14463 |
98 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4790 |
0 |
0 |
T104 |
64799 |
537 |
0 |
0 |
T121 |
9002 |
39 |
0 |
0 |
T124 |
7076 |
1 |
0 |
0 |
T127 |
10178 |
90 |
0 |
0 |
T131 |
4040 |
48 |
0 |
0 |
T146 |
6969 |
33 |
0 |
0 |
T158 |
9535 |
6 |
0 |
0 |
T159 |
8510 |
24 |
0 |
0 |
T160 |
180040 |
433 |
0 |
0 |
T161 |
14463 |
90 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4574 |
0 |
0 |
T104 |
64799 |
373 |
0 |
0 |
T121 |
9002 |
12 |
0 |
0 |
T124 |
7076 |
107 |
0 |
0 |
T127 |
10178 |
30 |
0 |
0 |
T131 |
4040 |
6 |
0 |
0 |
T158 |
9535 |
14 |
0 |
0 |
T159 |
8510 |
10 |
0 |
0 |
T160 |
180040 |
443 |
0 |
0 |
T161 |
14463 |
11 |
0 |
0 |
T162 |
36718 |
321 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4262 |
0 |
0 |
T104 |
64799 |
469 |
0 |
0 |
T121 |
9002 |
6 |
0 |
0 |
T124 |
7076 |
117 |
0 |
0 |
T127 |
10178 |
26 |
0 |
0 |
T131 |
4040 |
7 |
0 |
0 |
T146 |
6969 |
21 |
0 |
0 |
T158 |
9535 |
59 |
0 |
0 |
T159 |
8510 |
12 |
0 |
0 |
T160 |
180040 |
478 |
0 |
0 |
T161 |
14463 |
21 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4938 |
0 |
0 |
T104 |
64799 |
557 |
0 |
0 |
T121 |
9002 |
44 |
0 |
0 |
T124 |
7076 |
10 |
0 |
0 |
T127 |
10178 |
24 |
0 |
0 |
T131 |
4040 |
2 |
0 |
0 |
T146 |
6969 |
12 |
0 |
0 |
T158 |
9535 |
2 |
0 |
0 |
T159 |
8510 |
4 |
0 |
0 |
T160 |
180040 |
497 |
0 |
0 |
T161 |
14463 |
40 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4593 |
0 |
0 |
T103 |
20002 |
8 |
0 |
0 |
T104 |
64799 |
457 |
0 |
0 |
T121 |
9002 |
65 |
0 |
0 |
T124 |
7076 |
61 |
0 |
0 |
T127 |
10178 |
57 |
0 |
0 |
T131 |
4040 |
2 |
0 |
0 |
T146 |
6969 |
51 |
0 |
0 |
T160 |
180040 |
423 |
0 |
0 |
T161 |
14463 |
47 |
0 |
0 |
T162 |
36718 |
85 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4328 |
0 |
0 |
T104 |
64799 |
485 |
0 |
0 |
T121 |
9002 |
60 |
0 |
0 |
T124 |
7076 |
86 |
0 |
0 |
T127 |
10178 |
32 |
0 |
0 |
T131 |
4040 |
54 |
0 |
0 |
T146 |
6969 |
1 |
0 |
0 |
T158 |
9535 |
48 |
0 |
0 |
T159 |
8510 |
53 |
0 |
0 |
T160 |
180040 |
450 |
0 |
0 |
T161 |
14463 |
32 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4367 |
0 |
0 |
T104 |
64799 |
364 |
0 |
0 |
T121 |
9002 |
65 |
0 |
0 |
T124 |
7076 |
107 |
0 |
0 |
T127 |
10178 |
33 |
0 |
0 |
T131 |
4040 |
8 |
0 |
0 |
T146 |
6969 |
40 |
0 |
0 |
T158 |
9535 |
4 |
0 |
0 |
T159 |
8510 |
3 |
0 |
0 |
T160 |
180040 |
440 |
0 |
0 |
T161 |
14463 |
51 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4786 |
0 |
0 |
T104 |
64799 |
515 |
0 |
0 |
T121 |
9002 |
70 |
0 |
0 |
T124 |
7076 |
46 |
0 |
0 |
T127 |
10178 |
36 |
0 |
0 |
T131 |
4040 |
54 |
0 |
0 |
T146 |
6969 |
7 |
0 |
0 |
T158 |
9535 |
42 |
0 |
0 |
T159 |
8510 |
16 |
0 |
0 |
T160 |
180040 |
488 |
0 |
0 |
T161 |
14463 |
76 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4247 |
0 |
0 |
T104 |
64799 |
400 |
0 |
0 |
T121 |
9002 |
5 |
0 |
0 |
T124 |
7076 |
79 |
0 |
0 |
T127 |
10178 |
10 |
0 |
0 |
T131 |
4040 |
2 |
0 |
0 |
T146 |
6969 |
17 |
0 |
0 |
T158 |
9535 |
20 |
0 |
0 |
T159 |
8510 |
28 |
0 |
0 |
T160 |
180040 |
423 |
0 |
0 |
T161 |
14463 |
27 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4727 |
0 |
0 |
T104 |
64799 |
463 |
0 |
0 |
T121 |
9002 |
41 |
0 |
0 |
T124 |
7076 |
6 |
0 |
0 |
T127 |
10178 |
21 |
0 |
0 |
T131 |
4040 |
6 |
0 |
0 |
T146 |
6969 |
18 |
0 |
0 |
T158 |
9535 |
36 |
0 |
0 |
T159 |
8510 |
52 |
0 |
0 |
T160 |
180040 |
423 |
0 |
0 |
T161 |
14463 |
96 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4726 |
0 |
0 |
T104 |
64799 |
562 |
0 |
0 |
T121 |
9002 |
53 |
0 |
0 |
T124 |
7076 |
12 |
0 |
0 |
T127 |
10178 |
13 |
0 |
0 |
T131 |
4040 |
8 |
0 |
0 |
T146 |
6969 |
43 |
0 |
0 |
T158 |
9535 |
70 |
0 |
0 |
T159 |
8510 |
60 |
0 |
0 |
T160 |
180040 |
493 |
0 |
0 |
T161 |
14463 |
32 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
5070 |
0 |
0 |
T102 |
15806 |
3 |
0 |
0 |
T104 |
64799 |
564 |
0 |
0 |
T121 |
9002 |
46 |
0 |
0 |
T124 |
7076 |
111 |
0 |
0 |
T127 |
10178 |
115 |
0 |
0 |
T131 |
4040 |
2 |
0 |
0 |
T146 |
6969 |
6 |
0 |
0 |
T158 |
9535 |
64 |
0 |
0 |
T159 |
8510 |
45 |
0 |
0 |
T160 |
180040 |
422 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4185 |
0 |
0 |
T104 |
64799 |
470 |
0 |
0 |
T121 |
9002 |
7 |
0 |
0 |
T124 |
7076 |
12 |
0 |
0 |
T127 |
10178 |
41 |
0 |
0 |
T131 |
4040 |
7 |
0 |
0 |
T146 |
6969 |
14 |
0 |
0 |
T158 |
9535 |
5 |
0 |
0 |
T159 |
8510 |
16 |
0 |
0 |
T160 |
180040 |
380 |
0 |
0 |
T161 |
14463 |
73 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4764 |
0 |
0 |
T104 |
64799 |
660 |
0 |
0 |
T121 |
9002 |
3 |
0 |
0 |
T124 |
7076 |
3 |
0 |
0 |
T127 |
10178 |
59 |
0 |
0 |
T131 |
4040 |
2 |
0 |
0 |
T146 |
6969 |
4 |
0 |
0 |
T158 |
9535 |
67 |
0 |
0 |
T159 |
8510 |
4 |
0 |
0 |
T160 |
180040 |
427 |
0 |
0 |
T161 |
14463 |
1 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4583 |
0 |
0 |
T104 |
64799 |
508 |
0 |
0 |
T121 |
9002 |
91 |
0 |
0 |
T124 |
7076 |
48 |
0 |
0 |
T127 |
10178 |
4 |
0 |
0 |
T131 |
4040 |
4 |
0 |
0 |
T146 |
6969 |
5 |
0 |
0 |
T158 |
9535 |
14 |
0 |
0 |
T159 |
8510 |
35 |
0 |
0 |
T160 |
180040 |
499 |
0 |
0 |
T161 |
14463 |
51 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4599 |
0 |
0 |
T104 |
64799 |
604 |
0 |
0 |
T121 |
9002 |
45 |
0 |
0 |
T124 |
7076 |
48 |
0 |
0 |
T127 |
10178 |
26 |
0 |
0 |
T131 |
4040 |
47 |
0 |
0 |
T146 |
6969 |
23 |
0 |
0 |
T158 |
9535 |
3 |
0 |
0 |
T159 |
8510 |
62 |
0 |
0 |
T160 |
180040 |
466 |
0 |
0 |
T161 |
14463 |
57 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4383 |
0 |
0 |
T104 |
64799 |
657 |
0 |
0 |
T121 |
9002 |
86 |
0 |
0 |
T124 |
7076 |
67 |
0 |
0 |
T127 |
10178 |
66 |
0 |
0 |
T131 |
4040 |
47 |
0 |
0 |
T146 |
6969 |
11 |
0 |
0 |
T158 |
9535 |
15 |
0 |
0 |
T159 |
8510 |
40 |
0 |
0 |
T160 |
180040 |
418 |
0 |
0 |
T161 |
14463 |
51 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
5483 |
0 |
0 |
T103 |
20002 |
1 |
0 |
0 |
T104 |
64799 |
726 |
0 |
0 |
T121 |
9002 |
111 |
0 |
0 |
T124 |
7076 |
91 |
0 |
0 |
T127 |
10178 |
52 |
0 |
0 |
T131 |
4040 |
2 |
0 |
0 |
T146 |
6969 |
49 |
0 |
0 |
T158 |
9535 |
76 |
0 |
0 |
T159 |
8510 |
69 |
0 |
0 |
T160 |
180040 |
443 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4547 |
0 |
0 |
T104 |
64799 |
667 |
0 |
0 |
T113 |
11864 |
8 |
0 |
0 |
T121 |
9002 |
5 |
0 |
0 |
T124 |
7076 |
13 |
0 |
0 |
T127 |
10178 |
3 |
0 |
0 |
T131 |
4040 |
5 |
0 |
0 |
T146 |
6969 |
13 |
0 |
0 |
T158 |
9535 |
26 |
0 |
0 |
T159 |
8510 |
10 |
0 |
0 |
T160 |
180040 |
443 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4864 |
0 |
0 |
T104 |
64799 |
630 |
0 |
0 |
T121 |
9002 |
55 |
0 |
0 |
T124 |
7076 |
102 |
0 |
0 |
T127 |
10178 |
54 |
0 |
0 |
T131 |
4040 |
41 |
0 |
0 |
T146 |
6969 |
33 |
0 |
0 |
T158 |
9535 |
10 |
0 |
0 |
T159 |
8510 |
4 |
0 |
0 |
T160 |
180040 |
455 |
0 |
0 |
T161 |
14463 |
76 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4255 |
0 |
0 |
T104 |
64799 |
512 |
0 |
0 |
T121 |
9002 |
39 |
0 |
0 |
T124 |
7076 |
72 |
0 |
0 |
T127 |
10178 |
48 |
0 |
0 |
T131 |
4040 |
2 |
0 |
0 |
T146 |
6969 |
39 |
0 |
0 |
T158 |
9535 |
29 |
0 |
0 |
T159 |
8510 |
8 |
0 |
0 |
T160 |
180040 |
436 |
0 |
0 |
T161 |
14463 |
36 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4697 |
0 |
0 |
T104 |
64799 |
646 |
0 |
0 |
T121 |
9002 |
55 |
0 |
0 |
T127 |
10178 |
34 |
0 |
0 |
T131 |
4040 |
56 |
0 |
0 |
T146 |
6969 |
30 |
0 |
0 |
T158 |
9535 |
55 |
0 |
0 |
T159 |
8510 |
22 |
0 |
0 |
T160 |
180040 |
495 |
0 |
0 |
T161 |
14463 |
23 |
0 |
0 |
T162 |
36718 |
195 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2307 |
0 |
0 |
T103 |
20002 |
5 |
0 |
0 |
T104 |
64799 |
101 |
0 |
0 |
T121 |
9002 |
18 |
0 |
0 |
T124 |
7076 |
17 |
0 |
0 |
T127 |
10178 |
13 |
0 |
0 |
T131 |
4040 |
3 |
0 |
0 |
T146 |
6969 |
39 |
0 |
0 |
T158 |
9535 |
11 |
0 |
0 |
T159 |
8510 |
7 |
0 |
0 |
T160 |
180040 |
390 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2428 |
0 |
0 |
T104 |
64799 |
107 |
0 |
0 |
T113 |
11864 |
5 |
0 |
0 |
T121 |
9002 |
11 |
0 |
0 |
T124 |
7076 |
17 |
0 |
0 |
T127 |
10178 |
10 |
0 |
0 |
T146 |
6969 |
31 |
0 |
0 |
T158 |
9535 |
18 |
0 |
0 |
T159 |
8510 |
3 |
0 |
0 |
T160 |
180040 |
468 |
0 |
0 |
T161 |
14463 |
13 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2441 |
0 |
0 |
T104 |
64799 |
111 |
0 |
0 |
T121 |
9002 |
8 |
0 |
0 |
T124 |
7076 |
16 |
0 |
0 |
T127 |
10178 |
7 |
0 |
0 |
T131 |
4040 |
4 |
0 |
0 |
T146 |
6969 |
30 |
0 |
0 |
T159 |
8510 |
9 |
0 |
0 |
T160 |
180040 |
527 |
0 |
0 |
T161 |
14463 |
31 |
0 |
0 |
T162 |
36718 |
52 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2454 |
0 |
0 |
T99 |
19521 |
8 |
0 |
0 |
T104 |
64799 |
119 |
0 |
0 |
T121 |
9002 |
12 |
0 |
0 |
T124 |
7076 |
10 |
0 |
0 |
T127 |
10178 |
6 |
0 |
0 |
T131 |
4040 |
8 |
0 |
0 |
T146 |
6969 |
29 |
0 |
0 |
T158 |
9535 |
6 |
0 |
0 |
T159 |
8510 |
2 |
0 |
0 |
T160 |
180040 |
449 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2747 |
0 |
0 |
T104 |
64799 |
212 |
0 |
0 |
T121 |
9002 |
20 |
0 |
0 |
T124 |
7076 |
16 |
0 |
0 |
T127 |
10178 |
5 |
0 |
0 |
T131 |
4040 |
5 |
0 |
0 |
T146 |
6969 |
24 |
0 |
0 |
T158 |
9535 |
1 |
0 |
0 |
T159 |
8510 |
4 |
0 |
0 |
T160 |
180040 |
476 |
0 |
0 |
T161 |
14463 |
29 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
4094 |
0 |
0 |
T20 |
7144 |
17 |
0 |
0 |
T38 |
0 |
18 |
0 |
0 |
T136 |
0 |
38 |
0 |
0 |
T163 |
0 |
32 |
0 |
0 |
T164 |
0 |
51 |
0 |
0 |
T165 |
0 |
8 |
0 |
0 |
T166 |
0 |
50 |
0 |
0 |
T167 |
0 |
19 |
0 |
0 |
T168 |
0 |
18 |
0 |
0 |
T169 |
0 |
18 |
0 |
0 |
T170 |
1770 |
0 |
0 |
0 |
T171 |
9605 |
0 |
0 |
0 |
T172 |
9969 |
0 |
0 |
0 |
T173 |
1714 |
0 |
0 |
0 |
T174 |
2776 |
0 |
0 |
0 |
T175 |
63066 |
0 |
0 |
0 |
T176 |
21702 |
0 |
0 |
0 |
T177 |
1283 |
0 |
0 |
0 |
T178 |
72526 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2373 |
0 |
0 |
T104 |
64799 |
145 |
0 |
0 |
T121 |
9002 |
10 |
0 |
0 |
T124 |
7076 |
11 |
0 |
0 |
T127 |
10178 |
2 |
0 |
0 |
T131 |
4040 |
4 |
0 |
0 |
T146 |
6969 |
20 |
0 |
0 |
T158 |
9535 |
6 |
0 |
0 |
T160 |
180040 |
446 |
0 |
0 |
T161 |
14463 |
6 |
0 |
0 |
T162 |
36718 |
52 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2301 |
0 |
0 |
T104 |
64799 |
154 |
0 |
0 |
T121 |
9002 |
14 |
0 |
0 |
T124 |
7076 |
2 |
0 |
0 |
T127 |
10178 |
20 |
0 |
0 |
T131 |
4040 |
3 |
0 |
0 |
T146 |
6969 |
27 |
0 |
0 |
T158 |
9535 |
8 |
0 |
0 |
T159 |
8510 |
13 |
0 |
0 |
T160 |
180040 |
405 |
0 |
0 |
T161 |
14463 |
14 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2195 |
0 |
0 |
T104 |
64799 |
63 |
0 |
0 |
T121 |
9002 |
10 |
0 |
0 |
T124 |
7076 |
8 |
0 |
0 |
T127 |
10178 |
16 |
0 |
0 |
T146 |
6969 |
30 |
0 |
0 |
T158 |
9535 |
11 |
0 |
0 |
T159 |
8510 |
8 |
0 |
0 |
T160 |
180040 |
434 |
0 |
0 |
T161 |
14463 |
10 |
0 |
0 |
T162 |
36718 |
33 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2172 |
0 |
0 |
T104 |
64799 |
70 |
0 |
0 |
T121 |
9002 |
11 |
0 |
0 |
T124 |
7076 |
3 |
0 |
0 |
T131 |
4040 |
7 |
0 |
0 |
T146 |
6969 |
14 |
0 |
0 |
T158 |
9535 |
10 |
0 |
0 |
T159 |
8510 |
7 |
0 |
0 |
T160 |
180040 |
461 |
0 |
0 |
T161 |
14463 |
13 |
0 |
0 |
T162 |
36718 |
33 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2201 |
0 |
0 |
T104 |
64799 |
68 |
0 |
0 |
T124 |
7076 |
9 |
0 |
0 |
T127 |
10178 |
13 |
0 |
0 |
T131 |
4040 |
8 |
0 |
0 |
T146 |
6969 |
18 |
0 |
0 |
T158 |
9535 |
7 |
0 |
0 |
T159 |
8510 |
3 |
0 |
0 |
T160 |
180040 |
453 |
0 |
0 |
T161 |
14463 |
10 |
0 |
0 |
T162 |
36718 |
40 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2132 |
0 |
0 |
T102 |
15806 |
4 |
0 |
0 |
T104 |
64799 |
74 |
0 |
0 |
T121 |
9002 |
6 |
0 |
0 |
T124 |
7076 |
13 |
0 |
0 |
T131 |
4040 |
5 |
0 |
0 |
T146 |
6969 |
38 |
0 |
0 |
T158 |
9535 |
6 |
0 |
0 |
T159 |
8510 |
12 |
0 |
0 |
T160 |
180040 |
433 |
0 |
0 |
T161 |
14463 |
9 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2745 |
0 |
0 |
T104 |
64799 |
188 |
0 |
0 |
T121 |
9002 |
3 |
0 |
0 |
T124 |
7076 |
27 |
0 |
0 |
T127 |
10178 |
12 |
0 |
0 |
T131 |
4040 |
3 |
0 |
0 |
T146 |
6969 |
13 |
0 |
0 |
T158 |
9535 |
23 |
0 |
0 |
T159 |
8510 |
12 |
0 |
0 |
T160 |
180040 |
455 |
0 |
0 |
T161 |
14463 |
14 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2128 |
0 |
0 |
T104 |
64799 |
72 |
0 |
0 |
T121 |
9002 |
8 |
0 |
0 |
T124 |
7076 |
3 |
0 |
0 |
T127 |
10178 |
4 |
0 |
0 |
T146 |
6969 |
31 |
0 |
0 |
T158 |
9535 |
3 |
0 |
0 |
T159 |
8510 |
15 |
0 |
0 |
T160 |
180040 |
405 |
0 |
0 |
T161 |
14463 |
21 |
0 |
0 |
T162 |
36718 |
26 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
3060 |
0 |
0 |
T104 |
64799 |
318 |
0 |
0 |
T121 |
9002 |
7 |
0 |
0 |
T124 |
7076 |
31 |
0 |
0 |
T131 |
4040 |
3 |
0 |
0 |
T146 |
6969 |
19 |
0 |
0 |
T158 |
9535 |
2 |
0 |
0 |
T159 |
8510 |
5 |
0 |
0 |
T160 |
180040 |
437 |
0 |
0 |
T161 |
14463 |
20 |
0 |
0 |
T162 |
36718 |
117 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2316 |
0 |
0 |
T104 |
64799 |
99 |
0 |
0 |
T121 |
9002 |
9 |
0 |
0 |
T124 |
7076 |
11 |
0 |
0 |
T127 |
10178 |
1 |
0 |
0 |
T146 |
6969 |
38 |
0 |
0 |
T158 |
9535 |
11 |
0 |
0 |
T159 |
8510 |
3 |
0 |
0 |
T160 |
180040 |
441 |
0 |
0 |
T161 |
14463 |
32 |
0 |
0 |
T179 |
9525 |
4 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2045 |
0 |
0 |
T104 |
64799 |
78 |
0 |
0 |
T124 |
7076 |
13 |
0 |
0 |
T127 |
10178 |
8 |
0 |
0 |
T131 |
4040 |
9 |
0 |
0 |
T146 |
6969 |
3 |
0 |
0 |
T158 |
9535 |
12 |
0 |
0 |
T159 |
8510 |
13 |
0 |
0 |
T160 |
180040 |
446 |
0 |
0 |
T161 |
14463 |
14 |
0 |
0 |
T162 |
36718 |
35 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2288 |
0 |
0 |
T104 |
64799 |
66 |
0 |
0 |
T124 |
7076 |
4 |
0 |
0 |
T127 |
10178 |
17 |
0 |
0 |
T131 |
4040 |
9 |
0 |
0 |
T146 |
6969 |
3 |
0 |
0 |
T158 |
9535 |
7 |
0 |
0 |
T159 |
8510 |
22 |
0 |
0 |
T160 |
180040 |
486 |
0 |
0 |
T161 |
14463 |
12 |
0 |
0 |
T162 |
36718 |
41 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2193 |
0 |
0 |
T104 |
64799 |
86 |
0 |
0 |
T121 |
9002 |
10 |
0 |
0 |
T124 |
7076 |
7 |
0 |
0 |
T127 |
10178 |
6 |
0 |
0 |
T131 |
4040 |
4 |
0 |
0 |
T146 |
6969 |
6 |
0 |
0 |
T158 |
9535 |
3 |
0 |
0 |
T159 |
8510 |
5 |
0 |
0 |
T160 |
180040 |
440 |
0 |
0 |
T161 |
14463 |
10 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2231 |
0 |
0 |
T102 |
15806 |
8 |
0 |
0 |
T104 |
64799 |
83 |
0 |
0 |
T121 |
9002 |
1 |
0 |
0 |
T124 |
7076 |
6 |
0 |
0 |
T127 |
10178 |
5 |
0 |
0 |
T146 |
6969 |
10 |
0 |
0 |
T158 |
9535 |
3 |
0 |
0 |
T159 |
8510 |
17 |
0 |
0 |
T160 |
180040 |
455 |
0 |
0 |
T161 |
14463 |
6 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2207 |
0 |
0 |
T104 |
64799 |
85 |
0 |
0 |
T121 |
9002 |
4 |
0 |
0 |
T124 |
7076 |
7 |
0 |
0 |
T127 |
10178 |
2 |
0 |
0 |
T131 |
4040 |
1 |
0 |
0 |
T146 |
6969 |
15 |
0 |
0 |
T158 |
9535 |
23 |
0 |
0 |
T159 |
8510 |
14 |
0 |
0 |
T160 |
180040 |
439 |
0 |
0 |
T161 |
14463 |
13 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428374673 |
2206 |
0 |
0 |
T104 |
64799 |
74 |
0 |
0 |
T121 |
9002 |
11 |
0 |
0 |
T124 |
7076 |
7 |
0 |
0 |
T127 |
10178 |
10 |
0 |
0 |
T131 |
4040 |
1 |
0 |
0 |
T146 |
6969 |
62 |
0 |
0 |
T158 |
9535 |
19 |
0 |
0 |
T159 |
8510 |
24 |
0 |
0 |
T160 |
180040 |
441 |
0 |
0 |
T161 |
14463 |
14 |
0 |
0 |