Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3555882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4317253

1

T1

1897

T2

50

T3

14441

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4284652	1			T1	2037		T2	181		T3	7786
values[0x0]	1793509	1			T1	434		T2	33		T3	6717
values[0x1]	1794974	1			T1	459		T2	27		T3	6867

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2524850	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5348285

1

T1

2099

T2

101

T3

16538

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30588	1			T1	5		T2	1		T3	73
valid_sources[0x01]	27651	1			T1	18		T3	81		T4	5
valid_sources[0x02]	31152	1			T1	13		T2	4		T3	80
valid_sources[0x03]	31330	1			T1	17		T3	91		T4	4
valid_sources[0x04]	42832	1			T1	7		T3	72		T4	18
valid_sources[0x05]	33577	1			T1	6		T2	1		T3	69
valid_sources[0x06]	26132	1			T1	16		T3	77		T4	2
valid_sources[0x07]	27794	1			T1	14		T3	101		T5	22
valid_sources[0x08]	30715	1			T1	10		T2	5		T3	73
valid_sources[0x09]	28314	1			T1	7		T2	9		T3	90
valid_sources[0x0a]	28418	1			T1	8		T2	2		T3	86
valid_sources[0x0b]	30953	1			T1	7		T3	93		T4	8
valid_sources[0x0c]	28703	1			T1	7		T2	1		T3	89
valid_sources[0x0d]	28281	1			T1	13		T3	80		T4	3
valid_sources[0x0e]	28850	1			T1	1		T2	3		T3	86
valid_sources[0x0f]	29543	1			T1	6		T3	76		T4	14
valid_sources[0x10]	32693	1			T1	3		T3	75		T4	7
valid_sources[0x11]	28667	1			T1	12		T3	80		T5	22
valid_sources[0x12]	31268	1			T1	3		T2	1		T3	76
valid_sources[0x13]	30793	1			T1	5		T3	90		T4	6
valid_sources[0x14]	30391	1			T1	15		T3	82		T4	8
valid_sources[0x15]	27024	1			T1	10		T3	70		T4	21
valid_sources[0x16]	28610	1			T1	13		T2	2		T3	84
valid_sources[0x17]	28272	1			T1	5		T3	91		T4	20
valid_sources[0x18]	33274	1			T1	11		T3	99		T4	10
valid_sources[0x19]	31055	1			T1	9		T3	84		T4	1
valid_sources[0x1a]	29294	1			T1	4		T3	58		T4	35
valid_sources[0x1b]	29310	1			T1	19		T2	1		T3	58
valid_sources[0x1c]	32383	1			T1	15		T2	1		T3	88
valid_sources[0x1d]	32952	1			T1	12		T3	56		T4	30
valid_sources[0x1e]	38088	1			T1	13		T2	1		T3	92
valid_sources[0x1f]	29866	1			T1	3		T3	76		T4	5
valid_sources[0x20]	30709	1			T1	12		T3	78		T4	13
valid_sources[0x21]	27275	1			T1	21		T3	96		T4	30
valid_sources[0x22]	29153	1			T1	11		T3	67		T4	13
valid_sources[0x23]	34917	1			T2	1		T3	79		T4	15
valid_sources[0x24]	27875	1			T1	8		T3	85		T4	6
valid_sources[0x25]	33565	1			T1	2		T3	82		T4	11
valid_sources[0x26]	28661	1			T1	13		T3	99		T4	5
valid_sources[0x27]	28969	1			T1	18		T3	62		T4	6
valid_sources[0x28]	29738	1			T1	8		T3	61		T5	38
valid_sources[0x29]	32433	1			T1	3		T3	82		T4	2
valid_sources[0x2a]	27016	1			T1	4		T3	83		T4	27
valid_sources[0x2b]	31750	1			T1	1		T2	4		T3	85
valid_sources[0x2c]	30079	1			T1	7		T3	86		T5	37
valid_sources[0x2d]	30535	1			T3	85		T4	5		T5	26
valid_sources[0x2e]	30443	1			T1	1		T3	79		T4	19
valid_sources[0x2f]	28718	1			T1	9		T3	94		T4	10
valid_sources[0x30]	28868	1			T2	1		T3	83		T4	13
valid_sources[0x31]	27242	1			T1	22		T2	1		T3	85
valid_sources[0x32]	28393	1			T1	1		T3	77		T4	10
valid_sources[0x33]	34355	1			T1	32		T3	74		T4	50
valid_sources[0x34]	27825	1			T2	9		T3	102		T4	24
valid_sources[0x35]	26668	1			T1	10		T3	80		T4	20
valid_sources[0x36]	27748	1			T1	6		T3	76		T4	10
valid_sources[0x37]	28999	1			T1	20		T3	74		T4	4
valid_sources[0x38]	25670	1			T1	7		T2	1		T3	79
valid_sources[0x39]	31259	1			T1	38		T2	5		T3	90
valid_sources[0x3a]	32256	1			T3	93		T4	18		T5	17
valid_sources[0x3b]	48561	1			T1	5		T2	1		T3	78
valid_sources[0x3c]	36471	1			T1	19		T3	79		T5	28
valid_sources[0x3d]	35390	1			T1	16		T3	83		T4	6
valid_sources[0x3e]	26755	1			T1	22		T3	99		T4	20
valid_sources[0x3f]	35181	1			T3	81		T5	73		T7	6
valid_sources[0x40]	35224	1			T1	2		T3	86		T4	10
valid_sources[0x41]	33076	1			T1	6		T2	2		T3	70
valid_sources[0x42]	30029	1			T1	3		T2	6		T3	90
valid_sources[0x43]	29041	1			T1	2		T3	98		T4	2
valid_sources[0x44]	32138	1			T1	15		T2	2		T3	68
valid_sources[0x45]	26835	1			T1	17		T3	64		T4	24
valid_sources[0x46]	30925	1			T1	27		T3	92		T4	5
valid_sources[0x47]	29214	1			T1	13		T3	94		T4	16
valid_sources[0x48]	29265	1			T1	19		T3	92		T4	11
valid_sources[0x49]	27600	1			T1	9		T3	92		T4	15
valid_sources[0x4a]	30444	1			T1	10		T2	6		T3	72
valid_sources[0x4b]	28547	1			T1	11		T3	55		T4	1
valid_sources[0x4c]	29146	1			T1	38		T2	1		T3	90
valid_sources[0x4d]	28901	1			T1	7		T3	98		T4	3
valid_sources[0x4e]	29513	1			T1	7		T2	1		T3	89
valid_sources[0x4f]	32750	1			T1	5		T3	84		T5	49
valid_sources[0x50]	30648	1			T1	5		T3	89		T4	31
valid_sources[0x51]	29092	1			T1	14		T3	84		T4	19
valid_sources[0x52]	32201	1			T1	2		T3	87		T4	13
valid_sources[0x53]	30567	1			T1	8		T3	91		T5	23
valid_sources[0x54]	26574	1			T1	9		T3	87		T4	2
valid_sources[0x55]	31861	1			T1	3		T2	1		T3	82
valid_sources[0x56]	27490	1			T1	12		T2	2		T3	91
valid_sources[0x57]	27851	1			T1	16		T2	9		T3	90
valid_sources[0x58]	28247	1			T1	8		T3	96		T4	5
valid_sources[0x59]	29027	1			T1	6		T2	3		T3	94
valid_sources[0x5a]	29696	1			T1	24		T3	86		T4	13
valid_sources[0x5b]	32160	1			T1	5		T2	4		T3	85
valid_sources[0x5c]	28500	1			T1	18		T2	3		T3	91
valid_sources[0x5d]	32548	1			T1	9		T3	74		T4	4
valid_sources[0x5e]	27948	1			T1	11		T2	1		T3	89
valid_sources[0x5f]	31426	1			T3	80		T4	6		T5	22
valid_sources[0x60]	26779	1			T1	5		T3	86		T4	9
valid_sources[0x61]	30957	1			T1	9		T3	77		T4	8
valid_sources[0x62]	31549	1			T1	8		T3	103		T4	2
valid_sources[0x63]	31115	1			T1	5		T2	3		T3	71
valid_sources[0x64]	28458	1			T1	43		T3	85		T4	10
valid_sources[0x65]	26465	1			T1	1		T2	5		T3	86
valid_sources[0x66]	29048	1			T1	26		T2	1		T3	94
valid_sources[0x67]	26545	1			T1	28		T3	87		T4	14
valid_sources[0x68]	29387	1			T1	12		T3	74		T4	3
valid_sources[0x69]	28463	1			T1	28		T3	82		T4	10
valid_sources[0x6a]	33498	1			T1	8		T3	74		T4	2
valid_sources[0x6b]	31308	1			T1	6		T3	96		T4	4
valid_sources[0x6c]	26805	1			T1	3		T3	77		T4	2
valid_sources[0x6d]	30390	1			T1	20		T3	104		T4	9
valid_sources[0x6e]	29624	1			T1	23		T3	78		T4	12
valid_sources[0x6f]	30555	1			T1	11		T3	96		T4	6
valid_sources[0x70]	27727	1			T1	3		T3	96		T5	22
valid_sources[0x71]	32531	1			T1	25		T2	2		T3	96
valid_sources[0x72]	26993	1			T1	13		T3	91		T4	8
valid_sources[0x73]	32171	1			T1	22		T3	77		T4	5
valid_sources[0x74]	35742	1			T1	15		T3	80		T4	8
valid_sources[0x75]	31339	1			T1	4		T3	67		T4	17
valid_sources[0x76]	29887	1			T1	10		T2	2		T3	88
valid_sources[0x77]	27002	1			T1	11		T2	2		T3	92
valid_sources[0x78]	31501	1			T1	2		T3	85		T4	7
valid_sources[0x79]	32051	1			T1	11		T3	71		T4	7
valid_sources[0x7a]	30712	1			T1	5		T3	83		T4	3
valid_sources[0x7b]	29143	1			T1	3		T3	93		T4	19
valid_sources[0x7c]	26779	1			T1	11		T3	83		T4	1
valid_sources[0x7d]	28915	1			T1	23		T3	73		T4	2
valid_sources[0x7e]	32744	1			T1	12		T3	70		T4	1
valid_sources[0x7f]	35173	1			T1	7		T3	76		T4	4
valid_sources[0x80]	31248	1			T1	23		T3	85		T4	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1053596

1

T1

1008

T2

34

T3

1793

values[0x0]

all_enables

biggest_size

1643630

1

T1

434

T2

13

T3

6272

values[0x1]

all_enables

biggest_size

1620027

1

T1

455

T2

3

T3

6376