Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3575664

1

T1

1033

T2

191

T3

6929

full_word

4316265

1

T1

1897

T2

50

T3

14441

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7891499	1			T1	2930		T2	241		T3	21370
auto[TlIntgErrCmd]	130	1			T99	12		T100	6		T101	11
auto[TlIntgErrData]	147	1			T99	4		T100	11		T101	11
auto[TlIntgErrBoth]	153	1			T99	14		T100	13		T101	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4286195

1

T1

2037

T2

181

T3

7786

auto[1]

3605734

1

T1

893

T2

60

T3

13584

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3232371	1			T1	1029		T2	147		T3	5993
auto[TlIntgErrNone]	partial	auto[1]	342902	1			T1	4		T2	44		T3	936
auto[TlIntgErrNone]	full_word	auto[0]	1053652	1			T1	1008		T2	34		T3	1793
auto[TlIntgErrNone]	full_word	auto[1]	3262574	1			T1	889		T2	16		T3	12648
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T99	7		T100	1		T101	7
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T99	4		T100	4		T101	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T99	1		T100	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T118	1		T122	1		T165	2
auto[TlIntgErrData]	partial	auto[0]	57	1			T99	1		T100	6		T101	4
auto[TlIntgErrData]	partial	auto[1]	71	1			T99	1		T100	4		T101	4
auto[TlIntgErrData]	full_word	auto[0]	11	1			T99	2		T100	1		T101	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T101	2		T122	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T99	5		T100	2		T101	6
auto[TlIntgErrBoth]	partial	auto[1]	88	1			T99	8		T100	11		T101	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T165	1		T172	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T99	1		T118	1		T165	1