Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443774846	3055945	0	0
DepthKnown_A	443774846	443639867	0	0
RvalidKnown_A	443774846	443639867	0	0
WreadyKnown_A	443774846	443639867	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	3055945	0	0
T1	90290	1663	0	0
T2	6372	0	0	0
T3	105811	11645	0	0
T4	32104	1663	0	0
T5	215971	6664	0	0
T6	1157	0	0	0
T7	104952	1663	0	0
T8	755483	3327	0	0
T9	655422	1666	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443774846	3219507	0	0
DepthKnown_A	443774846	443639867	0	0
RvalidKnown_A	443774846	443639867	0	0
WreadyKnown_A	443774846	443639867	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	3219507	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	9152	0	0
T4	32104	832	0	0
T5	215971	10042	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	2496	0	0
T9	655422	835	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443774846	189911	0	0
DepthKnown_A	443774846	443639867	0	0
RvalidKnown_A	443774846	443639867	0	0
WreadyKnown_A	443774846	443639867	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	189911	0	0
T3	105811	928	0	0
T4	32104	0	0	0
T5	215971	403	0	0
T6	1157	0	0	0
T7	104952	0	0	0
T8	755483	904	0	0
T9	655422	0	0	0
T10	54117	0	0	0
T11	11934	0	0	0
T12	6336	0	0	0
T23	0	1112	0	0
T24	0	13	0	0
T25	0	775	0	0
T30	0	128	0	0
T35	0	129	0	0
T36	0	64	0	0
T37	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443774846	447331	0	0
DepthKnown_A	443774846	443639867	0	0
RvalidKnown_A	443774846	443639867	0	0
WreadyKnown_A	443774846	443639867	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	447331	0	0
T3	105811	928	0	0
T4	32104	0	0	0
T5	215971	1817	0	0
T6	1157	0	0	0
T7	104952	0	0	0
T8	755483	904	0	0
T9	655422	0	0	0
T10	54117	0	0	0
T11	11934	0	0	0
T12	6336	0	0	0
T23	0	1108	0	0
T24	0	13	0	0
T25	0	2492	0	0
T30	0	128	0	0
T35	0	589	0	0
T36	0	64	0	0
T37	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443774846	6162656	0	0
DepthKnown_A	443774846	443639867	0	0
RvalidKnown_A	443774846	443639867	0	0
WreadyKnown_A	443774846	443639867	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	6162656	0	0
T1	90290	2102	0	0
T2	6372	241	0	0
T3	105811	11375	0	0
T4	32104	1644	0	0
T5	215971	3280	0	0
T6	1157	25	0	0
T7	104952	59	0	0
T8	755483	15052	0	0
T9	655422	1033	0	0
T10	54117	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443774846	12963555	0	0
DepthKnown_A	443774846	443639867	0	0
RvalidKnown_A	443774846	443639867	0	0
WreadyKnown_A	443774846	443639867	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	12963555	0	0
T1	90290	9049	0	0
T2	6372	760	0	0
T3	105811	11290	0	0
T4	32104	1644	0	0
T5	215971	14087	0	0
T6	1157	25	0	0
T7	104952	59	0	0
T8	755483	14964	0	0
T9	655422	4516	0	0
T10	54117	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443774846	443639867	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0