Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T23
1	0	Covered	T3,T8,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T14
1	0	Unreachable
1	1	Covered	T3,T8,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T5,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	755355805	596939640	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	755355805	3805086	0	0
GntImpliesValid_A	755355805	3805086	0	0
GrantKnown_A	755355805	596939640	0	0
IdxKnown_A	755355805	596939640	0	0
IndexIsCorrect_A	755355805	3805086	0	0
LockArbDecision_A	755355805	0	0	0
NoReadyValidNoGrant_A	755355805	0	0	0
ReadyAndValidImplyGrant_A	755355805	3805086	0	0
ReqAndReadyImplyGrant_A	755355805	3805086	0	0
ReqImpliesValid_A	755355805	3805086	0	0
ReqStaysHighUntilGranted0_M	755355805	0	0	0
RoundRobin_A	755355805	3	0	976
ValidKnown_A	755355805	596939640	0	0
gen_data_port_assertion.DataFlow_A	755355805	3805086	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	596939640	0	0
T1	104770	104693	0	0
T2	6372	6153	0	0
T3	307815	1111683	0	0
T4	61018	46436	0	0
T5	824779	519540	0	0
T6	1157	1090	0	0
T7	309176	206969	0	0
T8	1218079	980098	0	0
T9	841612	748149	0	0
T10	156293	105135	0	0
T11	71042	35368	0	0
T12	15232	7616	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3805086	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	307815	17637	0	0
T4	61018	832	0	0
T5	824779	6756	0	0
T6	1157	0	0	0
T7	309176	832	0	0
T8	1218079	9982	0	0
T9	841612	832	0	0
T10	156293	832	0	0
T11	71042	832	0	0
T12	15232	832	0	0
T23	0	12159	0	0
T24	0	52	0	0
T25	0	6462	0	0
T26	0	1361	0	0
T30	1216708	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T45	0	1911	0	0
T51	0	4619	0	0
T52	0	1032	0	0
T53	0	1280	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3805086	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	307815	17637	0	0
T4	61018	832	0	0
T5	824779	6756	0	0
T6	1157	0	0	0
T7	309176	832	0	0
T8	1218079	9982	0	0
T9	841612	832	0	0
T10	156293	832	0	0
T11	71042	832	0	0
T12	15232	832	0	0
T23	0	12159	0	0
T24	0	52	0	0
T25	0	6462	0	0
T26	0	1361	0	0
T30	1216708	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T45	0	1911	0	0
T51	0	4619	0	0
T52	0	1032	0	0
T53	0	1280	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	596939640	0	0
T1	104770	104693	0	0
T2	6372	6153	0	0
T3	307815	1111683	0	0
T4	61018	46436	0	0
T5	824779	519540	0	0
T6	1157	1090	0	0
T7	309176	206969	0	0
T8	1218079	980098	0	0
T9	841612	748149	0	0
T10	156293	105135	0	0
T11	71042	35368	0	0
T12	15232	7616	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	596939640	0	0
T1	104770	104693	0	0
T2	6372	6153	0	0
T3	307815	1111683	0	0
T4	61018	46436	0	0
T5	824779	519540	0	0
T6	1157	1090	0	0
T7	309176	206969	0	0
T8	1218079	980098	0	0
T9	841612	748149	0	0
T10	156293	105135	0	0
T11	71042	35368	0	0
T12	15232	7616	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3805086	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	307815	17637	0	0
T4	61018	832	0	0
T5	824779	6756	0	0
T6	1157	0	0	0
T7	309176	832	0	0
T8	1218079	9982	0	0
T9	841612	832	0	0
T10	156293	832	0	0
T11	71042	832	0	0
T12	15232	832	0	0
T23	0	12159	0	0
T24	0	52	0	0
T25	0	6462	0	0
T26	0	1361	0	0
T30	1216708	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T45	0	1911	0	0
T51	0	4619	0	0
T52	0	1032	0	0
T53	0	1280	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3805086	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	307815	17637	0	0
T4	61018	832	0	0
T5	824779	6756	0	0
T6	1157	0	0	0
T7	309176	832	0	0
T8	1218079	9982	0	0
T9	841612	832	0	0
T10	156293	832	0	0
T11	71042	832	0	0
T12	15232	832	0	0
T23	0	12159	0	0
T24	0	52	0	0
T25	0	6462	0	0
T26	0	1361	0	0
T30	1216708	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T45	0	1911	0	0
T51	0	4619	0	0
T52	0	1032	0	0
T53	0	1280	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3805086	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	307815	17637	0	0
T4	61018	832	0	0
T5	824779	6756	0	0
T6	1157	0	0	0
T7	309176	832	0	0
T8	1218079	9982	0	0
T9	841612	832	0	0
T10	156293	832	0	0
T11	71042	832	0	0
T12	15232	832	0	0
T23	0	12159	0	0
T24	0	52	0	0
T25	0	6462	0	0
T26	0	1361	0	0
T30	1216708	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T45	0	1911	0	0
T51	0	4619	0	0
T52	0	1032	0	0
T53	0	1280	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3805086	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	307815	17637	0	0
T4	61018	832	0	0
T5	824779	6756	0	0
T6	1157	0	0	0
T7	309176	832	0	0
T8	1218079	9982	0	0
T9	841612	832	0	0
T10	156293	832	0	0
T11	71042	832	0	0
T12	15232	832	0	0
T23	0	12159	0	0
T24	0	52	0	0
T25	0	6462	0	0
T26	0	1361	0	0
T30	1216708	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T45	0	1911	0	0
T51	0	4619	0	0
T52	0	1032	0	0
T53	0	1280	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3	0	976
T54	234355	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	22396	0	0	1
T58	13944	0	0	1
T59	46001	0	0	1
T60	2847	0	0	1
T61	7351	0	0	1
T62	9221	0	0	1
T63	39686	0	0	1
T64	1386	0	0	1
T65	1113	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	596939640	0	0
T1	104770	104693	0	0
T2	6372	6153	0	0
T3	307815	1111683	0	0
T4	61018	46436	0	0
T5	824779	519540	0	0
T6	1157	1090	0	0
T7	309176	206969	0	0
T8	1218079	980098	0	0
T9	841612	748149	0	0
T10	156293	105135	0	0
T11	71042	35368	0	0
T12	15232	7616	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755355805	3805086	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	307815	17637	0	0
T4	61018	832	0	0
T5	824779	6756	0	0
T6	1157	0	0	0
T7	309176	832	0	0
T8	1218079	9982	0	0
T9	841612	832	0	0
T10	156293	832	0	0
T11	71042	832	0	0
T12	15232	832	0	0
T23	0	12159	0	0
T24	0	52	0	0
T25	0	6462	0	0
T26	0	1361	0	0
T30	1216708	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T45	0	1911	0	0
T51	0	4619	0	0
T52	0	1032	0	0
T53	0	1280	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T23
1	0	Covered	T3,T8,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T14
1	0	Unreachable
1	1	Covered	T3,T8,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T8,T23
0	0	1	Unreachable
0	0	0	Covered	T3,T8,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	156985367	27152033	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	156985367	613118	0	0
GntImpliesValid_A	156985367	613118	0	0
GrantKnown_A	156985367	27152033	0	0
IdxKnown_A	156985367	27152033	0	0
IndexIsCorrect_A	156985367	613118	0	0
LockArbDecision_A	156985367	0	0	0
NoReadyValidNoGrant_A	156985367	0	0	0
ReadyAndValidImplyGrant_A	156985367	613118	0	0
ReqAndReadyImplyGrant_A	156985367	613118	0	0
ReqImpliesValid_A	156985367	613118	0	0
ReqStaysHighUntilGranted0_M	156985367	0	0	0
RoundRobin_A	156985367	0	0	0
ValidKnown_A	156985367	27152033	0	0
gen_data_port_assertion.DataFlow_A	156985367	613118	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	27152033	0	0
T3	101002	90600	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	140344	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	613118	0	0
T3	101002	2040	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	5105	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	3742	0	0
T24	0	52	0	0
T25	0	1222	0	0
T26	0	1361	0	0
T30	608354	0	0	0
T45	0	1911	0	0
T51	0	1021	0	0
T52	0	1032	0	0
T53	0	1280	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	613118	0	0
T3	101002	2040	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	5105	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	3742	0	0
T24	0	52	0	0
T25	0	1222	0	0
T26	0	1361	0	0
T30	608354	0	0	0
T45	0	1911	0	0
T51	0	1021	0	0
T52	0	1032	0	0
T53	0	1280	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	27152033	0	0
T3	101002	90600	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	140344	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	27152033	0	0
T3	101002	90600	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	140344	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	613118	0	0
T3	101002	2040	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	5105	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	3742	0	0
T24	0	52	0	0
T25	0	1222	0	0
T26	0	1361	0	0
T30	608354	0	0	0
T45	0	1911	0	0
T51	0	1021	0	0
T52	0	1032	0	0
T53	0	1280	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	613118	0	0
T3	101002	2040	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	5105	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	3742	0	0
T24	0	52	0	0
T25	0	1222	0	0
T26	0	1361	0	0
T30	608354	0	0	0
T45	0	1911	0	0
T51	0	1021	0	0
T52	0	1032	0	0
T53	0	1280	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	613118	0	0
T3	101002	2040	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	5105	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	3742	0	0
T24	0	52	0	0
T25	0	1222	0	0
T26	0	1361	0	0
T30	608354	0	0	0
T45	0	1911	0	0
T51	0	1021	0	0
T52	0	1032	0	0
T53	0	1280	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	613118	0	0
T3	101002	2040	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	5105	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	3742	0	0
T24	0	52	0	0
T25	0	1222	0	0
T26	0	1361	0	0
T30	608354	0	0	0
T45	0	1911	0	0
T51	0	1021	0	0
T52	0	1032	0	0
T53	0	1280	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	27152033	0	0
T3	101002	90600	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	140344	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T14	0	432	0	0
T23	0	370560	0	0
T24	0	584	0	0
T25	0	28080	0	0
T26	0	112568	0	0
T27	0	576	0	0
T28	0	720	0	0
T29	0	504	0	0
T30	608354	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	613118	0	0
T3	101002	2040	0	0
T4	14457	0	0	0
T5	304404	0	0	0
T7	102112	0	0	0
T8	231298	5105	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	3742	0	0
T24	0	52	0	0
T25	0	1222	0	0
T26	0	1361	0	0
T30	608354	0	0	0
T45	0	1911	0	0
T51	0	1021	0	0
T52	0	1032	0	0
T53	0	1280	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T5,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	156985367	128490697	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	156985367	837918	0	0
GntImpliesValid_A	156985367	837918	0	0
GrantKnown_A	156985367	128490697	0	0
IdxKnown_A	156985367	128490697	0	0
IndexIsCorrect_A	156985367	837918	0	0
LockArbDecision_A	156985367	0	0	0
NoReadyValidNoGrant_A	156985367	0	0	0
ReadyAndValidImplyGrant_A	156985367	837918	0	0
ReqAndReadyImplyGrant_A	156985367	837918	0	0
ReqImpliesValid_A	156985367	837918	0	0
ReqStaysHighUntilGranted0_M	156985367	0	0	0
RoundRobin_A	156985367	0	0	0
ValidKnown_A	156985367	128490697	0	0
gen_data_port_assertion.DataFlow_A	156985367	837918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	128490697	0	0
T1	14480	14480	0	0
T3	101002	915280	0	0
T4	14457	14400	0	0
T5	304404	303576	0	0
T7	102112	102112	0	0
T8	231298	84483	0	0
T9	93095	92784	0	0
T10	51088	51088	0	0
T11	35521	35368	0	0
T12	7616	7616	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	837918	0	0
T3	101002	4826	0	0
T4	14457	0	0	0
T5	304404	2177	0	0
T7	102112	0	0	0
T8	231298	6	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	8417	0	0
T25	0	5240	0	0
T30	608354	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T37	0	3083	0	0
T51	0	3598	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	837918	0	0
T3	101002	4826	0	0
T4	14457	0	0	0
T5	304404	2177	0	0
T7	102112	0	0	0
T8	231298	6	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	8417	0	0
T25	0	5240	0	0
T30	608354	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T37	0	3083	0	0
T51	0	3598	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	128490697	0	0
T1	14480	14480	0	0
T3	101002	915280	0	0
T4	14457	14400	0	0
T5	304404	303576	0	0
T7	102112	102112	0	0
T8	231298	84483	0	0
T9	93095	92784	0	0
T10	51088	51088	0	0
T11	35521	35368	0	0
T12	7616	7616	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	128490697	0	0
T1	14480	14480	0	0
T3	101002	915280	0	0
T4	14457	14400	0	0
T5	304404	303576	0	0
T7	102112	102112	0	0
T8	231298	84483	0	0
T9	93095	92784	0	0
T10	51088	51088	0	0
T11	35521	35368	0	0
T12	7616	7616	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	837918	0	0
T3	101002	4826	0	0
T4	14457	0	0	0
T5	304404	2177	0	0
T7	102112	0	0	0
T8	231298	6	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	8417	0	0
T25	0	5240	0	0
T30	608354	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T37	0	3083	0	0
T51	0	3598	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	837918	0	0
T3	101002	4826	0	0
T4	14457	0	0	0
T5	304404	2177	0	0
T7	102112	0	0	0
T8	231298	6	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	8417	0	0
T25	0	5240	0	0
T30	608354	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T37	0	3083	0	0
T51	0	3598	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	837918	0	0
T3	101002	4826	0	0
T4	14457	0	0	0
T5	304404	2177	0	0
T7	102112	0	0	0
T8	231298	6	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	8417	0	0
T25	0	5240	0	0
T30	608354	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T37	0	3083	0	0
T51	0	3598	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	837918	0	0
T3	101002	4826	0	0
T4	14457	0	0	0
T5	304404	2177	0	0
T7	102112	0	0	0
T8	231298	6	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	8417	0	0
T25	0	5240	0	0
T30	608354	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T37	0	3083	0	0
T51	0	3598	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	128490697	0	0
T1	14480	14480	0	0
T3	101002	915280	0	0
T4	14457	14400	0	0
T5	304404	303576	0	0
T7	102112	102112	0	0
T8	231298	84483	0	0
T9	93095	92784	0	0
T10	51088	51088	0	0
T11	35521	35368	0	0
T12	7616	7616	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156985367	837918	0	0
T3	101002	4826	0	0
T4	14457	0	0	0
T5	304404	2177	0	0
T7	102112	0	0	0
T8	231298	6	0	0
T9	93095	0	0	0
T10	51088	0	0	0
T11	35521	0	0	0
T12	7616	0	0	0
T23	0	8417	0	0
T25	0	5240	0	0
T30	608354	780	0	0
T35	0	521	0	0
T36	0	258	0	0
T37	0	3083	0	0
T51	0	3598	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441385071	441296910	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	441385071	2354050	0	0
GntImpliesValid_A	441385071	2354050	0	0
GrantKnown_A	441385071	441296910	0	0
IdxKnown_A	441385071	441296910	0	0
IndexIsCorrect_A	441385071	2354050	0	0
LockArbDecision_A	441385071	0	0	0
NoReadyValidNoGrant_A	441385071	0	0	0
ReadyAndValidImplyGrant_A	441385071	2354050	0	0
ReqAndReadyImplyGrant_A	441385071	2354050	0	0
ReqImpliesValid_A	441385071	2354050	0	0
ReqStaysHighUntilGranted0_M	441385071	0	0	0
RoundRobin_A	441385071	3	0	976
ValidKnown_A	441385071	441296910	0	0
gen_data_port_assertion.DataFlow_A	441385071	2354050	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	441296910	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	2354050	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	10771	0	0
T4	32104	832	0	0
T5	215971	4579	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	4871	0	0
T9	655422	832	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	2354050	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	10771	0	0
T4	32104	832	0	0
T5	215971	4579	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	4871	0	0
T9	655422	832	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	441296910	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	441296910	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	2354050	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	10771	0	0
T4	32104	832	0	0
T5	215971	4579	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	4871	0	0
T9	655422	832	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	2354050	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	10771	0	0
T4	32104	832	0	0
T5	215971	4579	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	4871	0	0
T9	655422	832	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	2354050	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	10771	0	0
T4	32104	832	0	0
T5	215971	4579	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	4871	0	0
T9	655422	832	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	2354050	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	10771	0	0
T4	32104	832	0	0
T5	215971	4579	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	4871	0	0
T9	655422	832	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	3	0	976
T54	234355	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	22396	0	0	1
T58	13944	0	0	1
T59	46001	0	0	1
T60	2847	0	0	1
T61	7351	0	0	1
T62	9221	0	0	1
T63	39686	0	0	1
T64	1386	0	0	1
T65	1113	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	441296910	0	0
T1	90290	90213	0	0
T2	6372	6153	0	0
T3	105811	105803	0	0
T4	32104	32036	0	0
T5	215971	215964	0	0
T6	1157	1090	0	0
T7	104952	104857	0	0
T8	755483	755271	0	0
T9	655422	655365	0	0
T10	54117	54047	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441385071	2354050	0	0
T1	90290	832	0	0
T2	6372	0	0	0
T3	105811	10771	0	0
T4	32104	832	0	0
T5	215971	4579	0	0
T6	1157	0	0	0
T7	104952	832	0	0
T8	755483	4871	0	0
T9	655422	832	0	0
T10	54117	832	0	0
T11	0	832	0	0
T12	0	832	0	0