Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
3390 |
0 |
0 |
T98 |
3748 |
7 |
0 |
0 |
T99 |
107450 |
4 |
0 |
0 |
T100 |
81196 |
5 |
0 |
0 |
T101 |
29263 |
6 |
0 |
0 |
T102 |
4977 |
3 |
0 |
0 |
T103 |
14369 |
4 |
0 |
0 |
T118 |
81663 |
4 |
0 |
0 |
T119 |
4832 |
2 |
0 |
0 |
T121 |
10275 |
1 |
0 |
0 |
T122 |
20990 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2287 |
0 |
0 |
T99 |
107450 |
118 |
0 |
0 |
T103 |
14369 |
39 |
0 |
0 |
T104 |
18465 |
4 |
0 |
0 |
T120 |
64850 |
83 |
0 |
0 |
T123 |
32222 |
23 |
0 |
0 |
T129 |
90826 |
239 |
0 |
0 |
T131 |
75201 |
487 |
0 |
0 |
T137 |
90799 |
204 |
0 |
0 |
T163 |
10030 |
9 |
0 |
0 |
T164 |
4459 |
2 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2236 |
0 |
0 |
T99 |
107450 |
108 |
0 |
0 |
T103 |
14369 |
25 |
0 |
0 |
T120 |
64850 |
109 |
0 |
0 |
T123 |
32222 |
31 |
0 |
0 |
T129 |
90826 |
192 |
0 |
0 |
T131 |
75201 |
545 |
0 |
0 |
T132 |
11809 |
6 |
0 |
0 |
T137 |
90799 |
193 |
0 |
0 |
T163 |
10030 |
14 |
0 |
0 |
T164 |
4459 |
2 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2845 |
0 |
0 |
T99 |
107450 |
231 |
0 |
0 |
T103 |
14369 |
23 |
0 |
0 |
T120 |
64850 |
147 |
0 |
0 |
T123 |
32222 |
23 |
0 |
0 |
T129 |
90826 |
206 |
0 |
0 |
T131 |
75201 |
493 |
0 |
0 |
T132 |
11809 |
24 |
0 |
0 |
T137 |
90799 |
229 |
0 |
0 |
T163 |
10030 |
8 |
0 |
0 |
T164 |
4459 |
9 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
12557 |
0 |
0 |
T99 |
107450 |
2435 |
0 |
0 |
T103 |
14369 |
120 |
0 |
0 |
T120 |
64850 |
988 |
0 |
0 |
T123 |
32222 |
297 |
0 |
0 |
T129 |
90826 |
190 |
0 |
0 |
T131 |
75201 |
485 |
0 |
0 |
T132 |
11809 |
371 |
0 |
0 |
T137 |
90799 |
234 |
0 |
0 |
T163 |
10030 |
201 |
0 |
0 |
T164 |
4459 |
120 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
12140 |
0 |
0 |
T99 |
107450 |
1993 |
0 |
0 |
T103 |
14369 |
129 |
0 |
0 |
T120 |
64850 |
1420 |
0 |
0 |
T123 |
32222 |
395 |
0 |
0 |
T129 |
90826 |
260 |
0 |
0 |
T131 |
75201 |
503 |
0 |
0 |
T132 |
11809 |
246 |
0 |
0 |
T137 |
90799 |
209 |
0 |
0 |
T163 |
10030 |
13 |
0 |
0 |
T164 |
4459 |
151 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
13469 |
0 |
0 |
T99 |
107450 |
2123 |
0 |
0 |
T103 |
14369 |
114 |
0 |
0 |
T120 |
64850 |
1745 |
0 |
0 |
T123 |
32222 |
377 |
0 |
0 |
T129 |
90826 |
233 |
0 |
0 |
T131 |
75201 |
526 |
0 |
0 |
T132 |
11809 |
226 |
0 |
0 |
T137 |
90799 |
194 |
0 |
0 |
T163 |
10030 |
5 |
0 |
0 |
T164 |
4459 |
128 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
12438 |
0 |
0 |
T99 |
107450 |
1855 |
0 |
0 |
T103 |
14369 |
17 |
0 |
0 |
T120 |
64850 |
1179 |
0 |
0 |
T123 |
32222 |
425 |
0 |
0 |
T129 |
90826 |
293 |
0 |
0 |
T131 |
75201 |
493 |
0 |
0 |
T132 |
11809 |
230 |
0 |
0 |
T137 |
90799 |
244 |
0 |
0 |
T163 |
10030 |
119 |
0 |
0 |
T164 |
4459 |
9 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
12807 |
0 |
0 |
T99 |
107450 |
2190 |
0 |
0 |
T103 |
14369 |
135 |
0 |
0 |
T120 |
64850 |
723 |
0 |
0 |
T123 |
32222 |
253 |
0 |
0 |
T129 |
90826 |
220 |
0 |
0 |
T131 |
75201 |
525 |
0 |
0 |
T132 |
11809 |
249 |
0 |
0 |
T137 |
90799 |
246 |
0 |
0 |
T163 |
10030 |
137 |
0 |
0 |
T164 |
4459 |
124 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
12900 |
0 |
0 |
T99 |
107450 |
1795 |
0 |
0 |
T103 |
14369 |
280 |
0 |
0 |
T120 |
64850 |
1221 |
0 |
0 |
T123 |
32222 |
352 |
0 |
0 |
T129 |
90826 |
232 |
0 |
0 |
T131 |
75201 |
454 |
0 |
0 |
T132 |
11809 |
124 |
0 |
0 |
T137 |
90799 |
188 |
0 |
0 |
T163 |
10030 |
178 |
0 |
0 |
T165 |
69002 |
1348 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
11481 |
0 |
0 |
T99 |
107450 |
1658 |
0 |
0 |
T103 |
14369 |
333 |
0 |
0 |
T120 |
64850 |
1200 |
0 |
0 |
T123 |
32222 |
363 |
0 |
0 |
T129 |
90826 |
236 |
0 |
0 |
T131 |
75201 |
540 |
0 |
0 |
T132 |
11809 |
113 |
0 |
0 |
T137 |
90799 |
206 |
0 |
0 |
T163 |
10030 |
143 |
0 |
0 |
T164 |
4459 |
9 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
11919 |
0 |
0 |
T99 |
107450 |
1432 |
0 |
0 |
T103 |
14369 |
258 |
0 |
0 |
T120 |
64850 |
885 |
0 |
0 |
T123 |
32222 |
165 |
0 |
0 |
T129 |
90826 |
211 |
0 |
0 |
T131 |
75201 |
510 |
0 |
0 |
T132 |
11809 |
102 |
0 |
0 |
T137 |
90799 |
203 |
0 |
0 |
T163 |
10030 |
199 |
0 |
0 |
T164 |
4459 |
149 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
5688 |
0 |
0 |
T99 |
107450 |
701 |
0 |
0 |
T103 |
14369 |
21 |
0 |
0 |
T120 |
64850 |
423 |
0 |
0 |
T123 |
32222 |
192 |
0 |
0 |
T129 |
90826 |
234 |
0 |
0 |
T131 |
75201 |
493 |
0 |
0 |
T132 |
11809 |
114 |
0 |
0 |
T137 |
90799 |
207 |
0 |
0 |
T163 |
10030 |
8 |
0 |
0 |
T164 |
4459 |
51 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6413 |
0 |
0 |
T99 |
107450 |
948 |
0 |
0 |
T103 |
14369 |
190 |
0 |
0 |
T120 |
64850 |
774 |
0 |
0 |
T123 |
32222 |
114 |
0 |
0 |
T129 |
90826 |
248 |
0 |
0 |
T131 |
75201 |
414 |
0 |
0 |
T132 |
11809 |
79 |
0 |
0 |
T137 |
90799 |
274 |
0 |
0 |
T163 |
10030 |
32 |
0 |
0 |
T164 |
4459 |
3 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6222 |
0 |
0 |
T99 |
107450 |
797 |
0 |
0 |
T103 |
14369 |
130 |
0 |
0 |
T107 |
13098 |
6 |
0 |
0 |
T120 |
64850 |
530 |
0 |
0 |
T123 |
32222 |
102 |
0 |
0 |
T129 |
90826 |
250 |
0 |
0 |
T131 |
75201 |
539 |
0 |
0 |
T137 |
90799 |
236 |
0 |
0 |
T163 |
10030 |
4 |
0 |
0 |
T164 |
4459 |
61 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
5819 |
0 |
0 |
T99 |
107450 |
643 |
0 |
0 |
T103 |
14369 |
78 |
0 |
0 |
T120 |
64850 |
354 |
0 |
0 |
T123 |
32222 |
134 |
0 |
0 |
T129 |
90826 |
225 |
0 |
0 |
T131 |
75201 |
467 |
0 |
0 |
T132 |
11809 |
22 |
0 |
0 |
T137 |
90799 |
228 |
0 |
0 |
T163 |
10030 |
43 |
0 |
0 |
T164 |
4459 |
5 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6665 |
0 |
0 |
T99 |
107450 |
884 |
0 |
0 |
T103 |
14369 |
51 |
0 |
0 |
T120 |
64850 |
774 |
0 |
0 |
T123 |
32222 |
199 |
0 |
0 |
T129 |
90826 |
242 |
0 |
0 |
T131 |
75201 |
531 |
0 |
0 |
T132 |
11809 |
67 |
0 |
0 |
T137 |
90799 |
203 |
0 |
0 |
T163 |
10030 |
33 |
0 |
0 |
T164 |
4459 |
52 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6991 |
0 |
0 |
T99 |
107450 |
994 |
0 |
0 |
T103 |
14369 |
27 |
0 |
0 |
T120 |
64850 |
656 |
0 |
0 |
T123 |
32222 |
234 |
0 |
0 |
T129 |
90826 |
219 |
0 |
0 |
T131 |
75201 |
531 |
0 |
0 |
T132 |
11809 |
72 |
0 |
0 |
T137 |
90799 |
260 |
0 |
0 |
T163 |
10030 |
35 |
0 |
0 |
T164 |
4459 |
45 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6098 |
0 |
0 |
T99 |
107450 |
716 |
0 |
0 |
T103 |
14369 |
58 |
0 |
0 |
T120 |
64850 |
492 |
0 |
0 |
T123 |
32222 |
112 |
0 |
0 |
T129 |
90826 |
235 |
0 |
0 |
T131 |
75201 |
455 |
0 |
0 |
T132 |
11809 |
149 |
0 |
0 |
T137 |
90799 |
248 |
0 |
0 |
T163 |
10030 |
69 |
0 |
0 |
T164 |
4459 |
55 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6182 |
0 |
0 |
T99 |
107450 |
599 |
0 |
0 |
T103 |
14369 |
35 |
0 |
0 |
T120 |
64850 |
551 |
0 |
0 |
T123 |
32222 |
112 |
0 |
0 |
T129 |
90826 |
227 |
0 |
0 |
T131 |
75201 |
553 |
0 |
0 |
T132 |
11809 |
57 |
0 |
0 |
T137 |
90799 |
263 |
0 |
0 |
T163 |
10030 |
11 |
0 |
0 |
T164 |
4459 |
30 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6555 |
0 |
0 |
T99 |
107450 |
898 |
0 |
0 |
T103 |
14369 |
69 |
0 |
0 |
T120 |
64850 |
330 |
0 |
0 |
T123 |
32222 |
160 |
0 |
0 |
T129 |
90826 |
263 |
0 |
0 |
T131 |
75201 |
500 |
0 |
0 |
T132 |
11809 |
114 |
0 |
0 |
T137 |
90799 |
246 |
0 |
0 |
T163 |
10030 |
24 |
0 |
0 |
T164 |
4459 |
58 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6173 |
0 |
0 |
T99 |
107450 |
846 |
0 |
0 |
T103 |
14369 |
160 |
0 |
0 |
T120 |
64850 |
347 |
0 |
0 |
T123 |
32222 |
94 |
0 |
0 |
T129 |
90826 |
244 |
0 |
0 |
T131 |
75201 |
508 |
0 |
0 |
T132 |
11809 |
38 |
0 |
0 |
T137 |
90799 |
247 |
0 |
0 |
T163 |
10030 |
41 |
0 |
0 |
T164 |
4459 |
2 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6354 |
0 |
0 |
T99 |
107450 |
996 |
0 |
0 |
T103 |
14369 |
22 |
0 |
0 |
T120 |
64850 |
373 |
0 |
0 |
T123 |
32222 |
114 |
0 |
0 |
T129 |
90826 |
244 |
0 |
0 |
T131 |
75201 |
520 |
0 |
0 |
T132 |
11809 |
130 |
0 |
0 |
T137 |
90799 |
228 |
0 |
0 |
T163 |
10030 |
61 |
0 |
0 |
T164 |
4459 |
63 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6426 |
0 |
0 |
T99 |
107450 |
779 |
0 |
0 |
T103 |
14369 |
89 |
0 |
0 |
T120 |
64850 |
433 |
0 |
0 |
T123 |
32222 |
144 |
0 |
0 |
T129 |
90826 |
207 |
0 |
0 |
T131 |
75201 |
527 |
0 |
0 |
T132 |
11809 |
144 |
0 |
0 |
T137 |
90799 |
234 |
0 |
0 |
T163 |
10030 |
63 |
0 |
0 |
T164 |
4459 |
1 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6795 |
0 |
0 |
T99 |
107450 |
734 |
0 |
0 |
T103 |
14369 |
85 |
0 |
0 |
T120 |
64850 |
572 |
0 |
0 |
T123 |
32222 |
146 |
0 |
0 |
T129 |
90826 |
223 |
0 |
0 |
T131 |
75201 |
533 |
0 |
0 |
T132 |
11809 |
141 |
0 |
0 |
T137 |
90799 |
198 |
0 |
0 |
T163 |
10030 |
17 |
0 |
0 |
T164 |
4459 |
5 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6562 |
0 |
0 |
T99 |
107450 |
908 |
0 |
0 |
T103 |
14369 |
26 |
0 |
0 |
T120 |
64850 |
744 |
0 |
0 |
T123 |
32222 |
129 |
0 |
0 |
T129 |
90826 |
211 |
0 |
0 |
T131 |
75201 |
619 |
0 |
0 |
T132 |
11809 |
111 |
0 |
0 |
T137 |
90799 |
195 |
0 |
0 |
T163 |
10030 |
86 |
0 |
0 |
T164 |
4459 |
41 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6448 |
0 |
0 |
T99 |
107450 |
702 |
0 |
0 |
T103 |
14369 |
148 |
0 |
0 |
T120 |
64850 |
658 |
0 |
0 |
T123 |
32222 |
49 |
0 |
0 |
T129 |
90826 |
222 |
0 |
0 |
T131 |
75201 |
526 |
0 |
0 |
T132 |
11809 |
56 |
0 |
0 |
T137 |
90799 |
222 |
0 |
0 |
T163 |
10030 |
69 |
0 |
0 |
T164 |
4459 |
51 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6367 |
0 |
0 |
T99 |
107450 |
775 |
0 |
0 |
T103 |
14369 |
124 |
0 |
0 |
T107 |
13098 |
2 |
0 |
0 |
T120 |
64850 |
551 |
0 |
0 |
T123 |
32222 |
128 |
0 |
0 |
T129 |
90826 |
235 |
0 |
0 |
T131 |
75201 |
516 |
0 |
0 |
T137 |
90799 |
204 |
0 |
0 |
T163 |
10030 |
43 |
0 |
0 |
T164 |
4459 |
2 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6423 |
0 |
0 |
T99 |
107450 |
879 |
0 |
0 |
T103 |
14369 |
27 |
0 |
0 |
T120 |
64850 |
442 |
0 |
0 |
T123 |
32222 |
174 |
0 |
0 |
T129 |
90826 |
258 |
0 |
0 |
T131 |
75201 |
506 |
0 |
0 |
T132 |
11809 |
97 |
0 |
0 |
T137 |
90799 |
213 |
0 |
0 |
T163 |
10030 |
71 |
0 |
0 |
T164 |
4459 |
37 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6215 |
0 |
0 |
T99 |
107450 |
691 |
0 |
0 |
T103 |
14369 |
71 |
0 |
0 |
T107 |
13098 |
2 |
0 |
0 |
T120 |
64850 |
457 |
0 |
0 |
T123 |
32222 |
211 |
0 |
0 |
T129 |
90826 |
258 |
0 |
0 |
T131 |
75201 |
521 |
0 |
0 |
T132 |
11809 |
17 |
0 |
0 |
T137 |
90799 |
230 |
0 |
0 |
T163 |
10030 |
41 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
5648 |
0 |
0 |
T99 |
107450 |
500 |
0 |
0 |
T103 |
14369 |
32 |
0 |
0 |
T120 |
64850 |
448 |
0 |
0 |
T123 |
32222 |
89 |
0 |
0 |
T129 |
90826 |
247 |
0 |
0 |
T131 |
75201 |
472 |
0 |
0 |
T132 |
11809 |
87 |
0 |
0 |
T137 |
90799 |
215 |
0 |
0 |
T163 |
10030 |
57 |
0 |
0 |
T164 |
4459 |
4 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6839 |
0 |
0 |
T99 |
107450 |
1023 |
0 |
0 |
T103 |
14369 |
71 |
0 |
0 |
T120 |
64850 |
533 |
0 |
0 |
T123 |
32222 |
222 |
0 |
0 |
T129 |
90826 |
253 |
0 |
0 |
T131 |
75201 |
555 |
0 |
0 |
T132 |
11809 |
52 |
0 |
0 |
T137 |
90799 |
192 |
0 |
0 |
T163 |
10030 |
35 |
0 |
0 |
T165 |
69002 |
687 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6629 |
0 |
0 |
T99 |
107450 |
818 |
0 |
0 |
T103 |
14369 |
58 |
0 |
0 |
T120 |
64850 |
511 |
0 |
0 |
T123 |
32222 |
216 |
0 |
0 |
T129 |
90826 |
221 |
0 |
0 |
T131 |
75201 |
497 |
0 |
0 |
T132 |
11809 |
57 |
0 |
0 |
T137 |
90799 |
230 |
0 |
0 |
T163 |
10030 |
75 |
0 |
0 |
T164 |
4459 |
2 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
5653 |
0 |
0 |
T99 |
107450 |
756 |
0 |
0 |
T103 |
14369 |
45 |
0 |
0 |
T120 |
64850 |
590 |
0 |
0 |
T123 |
32222 |
122 |
0 |
0 |
T129 |
90826 |
210 |
0 |
0 |
T131 |
75201 |
478 |
0 |
0 |
T132 |
11809 |
11 |
0 |
0 |
T137 |
90799 |
198 |
0 |
0 |
T163 |
10030 |
81 |
0 |
0 |
T164 |
4459 |
3 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
6505 |
0 |
0 |
T99 |
107450 |
870 |
0 |
0 |
T103 |
14369 |
100 |
0 |
0 |
T104 |
18465 |
3 |
0 |
0 |
T120 |
64850 |
539 |
0 |
0 |
T123 |
32222 |
203 |
0 |
0 |
T129 |
90826 |
226 |
0 |
0 |
T131 |
75201 |
535 |
0 |
0 |
T132 |
11809 |
85 |
0 |
0 |
T137 |
90799 |
203 |
0 |
0 |
T163 |
10030 |
100 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
5354 |
0 |
0 |
T99 |
107450 |
841 |
0 |
0 |
T103 |
14369 |
12 |
0 |
0 |
T104 |
18465 |
2 |
0 |
0 |
T120 |
64850 |
381 |
0 |
0 |
T123 |
32222 |
41 |
0 |
0 |
T129 |
90826 |
241 |
0 |
0 |
T131 |
75201 |
506 |
0 |
0 |
T137 |
90799 |
273 |
0 |
0 |
T163 |
10030 |
10 |
0 |
0 |
T164 |
4459 |
41 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2749 |
0 |
0 |
T99 |
107450 |
169 |
0 |
0 |
T103 |
14369 |
29 |
0 |
0 |
T120 |
64850 |
119 |
0 |
0 |
T123 |
32222 |
47 |
0 |
0 |
T129 |
90826 |
227 |
0 |
0 |
T131 |
75201 |
519 |
0 |
0 |
T132 |
11809 |
21 |
0 |
0 |
T137 |
90799 |
226 |
0 |
0 |
T163 |
10030 |
15 |
0 |
0 |
T164 |
4459 |
9 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2631 |
0 |
0 |
T99 |
107450 |
168 |
0 |
0 |
T103 |
14369 |
22 |
0 |
0 |
T107 |
13098 |
10 |
0 |
0 |
T120 |
64850 |
124 |
0 |
0 |
T123 |
32222 |
40 |
0 |
0 |
T129 |
90826 |
226 |
0 |
0 |
T131 |
75201 |
541 |
0 |
0 |
T137 |
90799 |
180 |
0 |
0 |
T163 |
10030 |
5 |
0 |
0 |
T164 |
4459 |
3 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2742 |
0 |
0 |
T99 |
107450 |
143 |
0 |
0 |
T103 |
14369 |
29 |
0 |
0 |
T120 |
64850 |
111 |
0 |
0 |
T123 |
32222 |
38 |
0 |
0 |
T129 |
90826 |
225 |
0 |
0 |
T131 |
75201 |
525 |
0 |
0 |
T132 |
11809 |
9 |
0 |
0 |
T137 |
90799 |
233 |
0 |
0 |
T163 |
10030 |
5 |
0 |
0 |
T164 |
4459 |
7 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2733 |
0 |
0 |
T99 |
107450 |
190 |
0 |
0 |
T103 |
14369 |
36 |
0 |
0 |
T120 |
64850 |
129 |
0 |
0 |
T123 |
32222 |
46 |
0 |
0 |
T129 |
90826 |
187 |
0 |
0 |
T131 |
75201 |
530 |
0 |
0 |
T132 |
11809 |
17 |
0 |
0 |
T137 |
90799 |
232 |
0 |
0 |
T163 |
10030 |
9 |
0 |
0 |
T164 |
4459 |
6 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
3263 |
0 |
0 |
T99 |
107450 |
290 |
0 |
0 |
T103 |
14369 |
38 |
0 |
0 |
T120 |
64850 |
166 |
0 |
0 |
T123 |
32222 |
40 |
0 |
0 |
T129 |
90826 |
248 |
0 |
0 |
T131 |
75201 |
528 |
0 |
0 |
T132 |
11809 |
17 |
0 |
0 |
T137 |
90799 |
232 |
0 |
0 |
T163 |
10030 |
25 |
0 |
0 |
T164 |
4459 |
14 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
5541 |
0 |
0 |
T2 |
6372 |
38 |
0 |
0 |
T3 |
105811 |
0 |
0 |
0 |
T4 |
32104 |
0 |
0 |
0 |
T5 |
215971 |
0 |
0 |
0 |
T6 |
1157 |
0 |
0 |
0 |
T7 |
104952 |
0 |
0 |
0 |
T8 |
755483 |
0 |
0 |
0 |
T9 |
655422 |
0 |
0 |
0 |
T10 |
54117 |
0 |
0 |
0 |
T11 |
11934 |
0 |
0 |
0 |
T15 |
0 |
39 |
0 |
0 |
T18 |
0 |
38 |
0 |
0 |
T20 |
0 |
21 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T50 |
0 |
24 |
0 |
0 |
T166 |
0 |
53 |
0 |
0 |
T167 |
0 |
6 |
0 |
0 |
T168 |
0 |
21 |
0 |
0 |
T169 |
0 |
38 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2529 |
0 |
0 |
T99 |
107450 |
164 |
0 |
0 |
T103 |
14369 |
20 |
0 |
0 |
T120 |
64850 |
128 |
0 |
0 |
T123 |
32222 |
40 |
0 |
0 |
T129 |
90826 |
192 |
0 |
0 |
T131 |
75201 |
544 |
0 |
0 |
T132 |
11809 |
14 |
0 |
0 |
T137 |
90799 |
248 |
0 |
0 |
T163 |
10030 |
13 |
0 |
0 |
T164 |
4459 |
3 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2584 |
0 |
0 |
T99 |
107450 |
151 |
0 |
0 |
T103 |
14369 |
22 |
0 |
0 |
T120 |
64850 |
72 |
0 |
0 |
T123 |
32222 |
25 |
0 |
0 |
T129 |
90826 |
217 |
0 |
0 |
T131 |
75201 |
545 |
0 |
0 |
T132 |
11809 |
16 |
0 |
0 |
T137 |
90799 |
258 |
0 |
0 |
T163 |
10030 |
5 |
0 |
0 |
T164 |
4459 |
14 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2126 |
0 |
0 |
T99 |
107450 |
98 |
0 |
0 |
T103 |
14369 |
23 |
0 |
0 |
T120 |
64850 |
77 |
0 |
0 |
T123 |
32222 |
14 |
0 |
0 |
T129 |
90826 |
250 |
0 |
0 |
T131 |
75201 |
505 |
0 |
0 |
T132 |
11809 |
6 |
0 |
0 |
T137 |
90799 |
215 |
0 |
0 |
T163 |
10030 |
16 |
0 |
0 |
T164 |
4459 |
2 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2360 |
0 |
0 |
T99 |
107450 |
107 |
0 |
0 |
T103 |
14369 |
26 |
0 |
0 |
T120 |
64850 |
90 |
0 |
0 |
T123 |
32222 |
17 |
0 |
0 |
T129 |
90826 |
173 |
0 |
0 |
T131 |
75201 |
567 |
0 |
0 |
T132 |
11809 |
17 |
0 |
0 |
T137 |
90799 |
193 |
0 |
0 |
T163 |
10030 |
16 |
0 |
0 |
T165 |
69002 |
84 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2304 |
0 |
0 |
T99 |
107450 |
118 |
0 |
0 |
T103 |
14369 |
22 |
0 |
0 |
T120 |
64850 |
77 |
0 |
0 |
T123 |
32222 |
33 |
0 |
0 |
T129 |
90826 |
241 |
0 |
0 |
T131 |
75201 |
482 |
0 |
0 |
T132 |
11809 |
19 |
0 |
0 |
T137 |
90799 |
220 |
0 |
0 |
T163 |
10030 |
11 |
0 |
0 |
T164 |
4459 |
1 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2207 |
0 |
0 |
T99 |
107450 |
112 |
0 |
0 |
T103 |
14369 |
29 |
0 |
0 |
T120 |
64850 |
75 |
0 |
0 |
T123 |
32222 |
7 |
0 |
0 |
T129 |
90826 |
208 |
0 |
0 |
T131 |
75201 |
543 |
0 |
0 |
T132 |
11809 |
14 |
0 |
0 |
T137 |
90799 |
227 |
0 |
0 |
T163 |
10030 |
13 |
0 |
0 |
T164 |
4459 |
3 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
3115 |
0 |
0 |
T99 |
107450 |
253 |
0 |
0 |
T103 |
14369 |
26 |
0 |
0 |
T120 |
64850 |
207 |
0 |
0 |
T123 |
32222 |
50 |
0 |
0 |
T129 |
90826 |
231 |
0 |
0 |
T131 |
75201 |
500 |
0 |
0 |
T132 |
11809 |
41 |
0 |
0 |
T137 |
90799 |
219 |
0 |
0 |
T163 |
10030 |
5 |
0 |
0 |
T164 |
4459 |
1 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2262 |
0 |
0 |
T99 |
107450 |
122 |
0 |
0 |
T103 |
14369 |
25 |
0 |
0 |
T120 |
64850 |
89 |
0 |
0 |
T123 |
32222 |
15 |
0 |
0 |
T129 |
90826 |
205 |
0 |
0 |
T131 |
75201 |
473 |
0 |
0 |
T132 |
11809 |
21 |
0 |
0 |
T137 |
90799 |
227 |
0 |
0 |
T163 |
10030 |
7 |
0 |
0 |
T164 |
4459 |
9 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
3623 |
0 |
0 |
T99 |
107450 |
372 |
0 |
0 |
T103 |
14369 |
33 |
0 |
0 |
T120 |
64850 |
229 |
0 |
0 |
T123 |
32222 |
68 |
0 |
0 |
T129 |
90826 |
258 |
0 |
0 |
T131 |
75201 |
541 |
0 |
0 |
T132 |
11809 |
7 |
0 |
0 |
T137 |
90799 |
232 |
0 |
0 |
T163 |
10030 |
15 |
0 |
0 |
T164 |
4459 |
18 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2540 |
0 |
0 |
T99 |
107450 |
148 |
0 |
0 |
T103 |
14369 |
30 |
0 |
0 |
T120 |
64850 |
101 |
0 |
0 |
T123 |
32222 |
30 |
0 |
0 |
T129 |
90826 |
210 |
0 |
0 |
T131 |
75201 |
603 |
0 |
0 |
T132 |
11809 |
12 |
0 |
0 |
T137 |
90799 |
254 |
0 |
0 |
T163 |
10030 |
6 |
0 |
0 |
T164 |
4459 |
8 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2071 |
0 |
0 |
T99 |
107450 |
90 |
0 |
0 |
T103 |
14369 |
28 |
0 |
0 |
T104 |
18465 |
3 |
0 |
0 |
T120 |
64850 |
86 |
0 |
0 |
T123 |
32222 |
20 |
0 |
0 |
T129 |
90826 |
194 |
0 |
0 |
T131 |
75201 |
507 |
0 |
0 |
T137 |
90799 |
220 |
0 |
0 |
T163 |
10030 |
3 |
0 |
0 |
T164 |
4459 |
3 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2237 |
0 |
0 |
T99 |
107450 |
115 |
0 |
0 |
T103 |
14369 |
23 |
0 |
0 |
T120 |
64850 |
73 |
0 |
0 |
T123 |
32222 |
13 |
0 |
0 |
T129 |
90826 |
215 |
0 |
0 |
T131 |
75201 |
482 |
0 |
0 |
T132 |
11809 |
10 |
0 |
0 |
T137 |
90799 |
225 |
0 |
0 |
T163 |
10030 |
18 |
0 |
0 |
T164 |
4459 |
8 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2207 |
0 |
0 |
T99 |
107450 |
138 |
0 |
0 |
T103 |
14369 |
17 |
0 |
0 |
T104 |
18465 |
3 |
0 |
0 |
T120 |
64850 |
72 |
0 |
0 |
T123 |
32222 |
28 |
0 |
0 |
T129 |
90826 |
237 |
0 |
0 |
T131 |
75201 |
518 |
0 |
0 |
T137 |
90799 |
216 |
0 |
0 |
T163 |
10030 |
14 |
0 |
0 |
T164 |
4459 |
4 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2213 |
0 |
0 |
T99 |
107450 |
114 |
0 |
0 |
T103 |
14369 |
32 |
0 |
0 |
T120 |
64850 |
71 |
0 |
0 |
T123 |
32222 |
21 |
0 |
0 |
T129 |
90826 |
229 |
0 |
0 |
T131 |
75201 |
493 |
0 |
0 |
T132 |
11809 |
9 |
0 |
0 |
T137 |
90799 |
197 |
0 |
0 |
T163 |
10030 |
9 |
0 |
0 |
T164 |
4459 |
4 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2130 |
0 |
0 |
T99 |
107450 |
116 |
0 |
0 |
T103 |
14369 |
22 |
0 |
0 |
T120 |
64850 |
55 |
0 |
0 |
T123 |
32222 |
10 |
0 |
0 |
T129 |
90826 |
219 |
0 |
0 |
T131 |
75201 |
510 |
0 |
0 |
T132 |
11809 |
7 |
0 |
0 |
T137 |
90799 |
246 |
0 |
0 |
T163 |
10030 |
4 |
0 |
0 |
T164 |
4459 |
2 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
443774846 |
2168 |
0 |
0 |
T99 |
107450 |
113 |
0 |
0 |
T103 |
14369 |
28 |
0 |
0 |
T120 |
64850 |
61 |
0 |
0 |
T123 |
32222 |
10 |
0 |
0 |
T129 |
90826 |
209 |
0 |
0 |
T131 |
75201 |
505 |
0 |
0 |
T132 |
11809 |
1 |
0 |
0 |
T137 |
90799 |
246 |
0 |
0 |
T163 |
10030 |
5 |
0 |
0 |
T164 |
4459 |
7 |
0 |
0 |