Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3475496	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4232809

1

T1

2593

T2

7309

T3

7158

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4259749	1			T1	3475		T2	2341		T3	12434
values[0x0]	1723268	1			T1	438		T2	3138		T3	442
values[0x1]	1725288	1			T1	465		T2	3018		T3	455

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2475498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5232807

1

T1

2941

T2

7583

T3

8389

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29932	1			T1	11		T2	14		T3	41
valid_sources[0x01]	29046	1			T1	44		T2	23		T3	67
valid_sources[0x02]	29387	1			T1	20		T2	24		T3	55
valid_sources[0x03]	29440	1			T1	6		T2	50		T3	60
valid_sources[0x04]	31505	1			T1	27		T2	31		T3	59
valid_sources[0x05]	27267	1			T1	8		T2	30		T3	51
valid_sources[0x06]	33004	1			T1	16		T2	25		T3	48
valid_sources[0x07]	31346	1			T1	3		T2	41		T3	53
valid_sources[0x08]	28258	1			T1	7		T2	37		T3	59
valid_sources[0x09]	38023	1			T1	9		T2	18		T3	48
valid_sources[0x0a]	30307	1			T1	22		T2	32		T3	68
valid_sources[0x0b]	30718	1			T1	16		T2	24		T3	46
valid_sources[0x0c]	31703	1			T1	41		T2	34		T3	63
valid_sources[0x0d]	40095	1			T1	27		T2	55		T3	49
valid_sources[0x0e]	28655	1			T1	9		T2	42		T3	44
valid_sources[0x0f]	29356	1			T1	7		T2	47		T3	59
valid_sources[0x10]	30068	1			T1	7		T2	30		T3	54
valid_sources[0x11]	30266	1			T1	36		T2	15		T3	63
valid_sources[0x12]	28015	1			T1	16		T2	38		T3	53
valid_sources[0x13]	27729	1			T1	11		T2	69		T3	40
valid_sources[0x14]	29256	1			T1	21		T2	24		T3	48
valid_sources[0x15]	30196	1			T1	20		T2	44		T3	51
valid_sources[0x16]	28344	1			T1	16		T2	28		T3	48
valid_sources[0x17]	29831	1			T1	27		T2	25		T3	59
valid_sources[0x18]	28553	1			T1	41		T2	29		T3	52
valid_sources[0x19]	29425	1			T1	12		T2	36		T3	44
valid_sources[0x1a]	28968	1			T1	16		T2	59		T3	60
valid_sources[0x1b]	30793	1			T1	22		T2	47		T3	42
valid_sources[0x1c]	29780	1			T1	4		T2	29		T3	39
valid_sources[0x1d]	30595	1			T1	12		T2	55		T3	57
valid_sources[0x1e]	28298	1			T1	12		T2	42		T3	67
valid_sources[0x1f]	28377	1			T1	2		T2	34		T3	42
valid_sources[0x20]	30623	1			T1	24		T2	25		T3	45
valid_sources[0x21]	29362	1			T1	7		T2	18		T3	73
valid_sources[0x22]	29561	1			T1	14		T2	29		T3	51
valid_sources[0x23]	28545	1			T1	1		T2	29		T3	48
valid_sources[0x24]	33044	1			T1	22		T2	37		T3	56
valid_sources[0x25]	29060	1			T1	8		T2	15		T3	41
valid_sources[0x26]	27323	1			T1	11		T2	23		T3	43
valid_sources[0x27]	29423	1			T1	22		T2	43		T3	45
valid_sources[0x28]	26448	1			T1	1		T2	29		T3	48
valid_sources[0x29]	29910	1			T1	12		T2	45		T3	57
valid_sources[0x2a]	30264	1			T1	14		T2	25		T3	53
valid_sources[0x2b]	28587	1			T1	24		T2	28		T3	58
valid_sources[0x2c]	28645	1			T1	5		T2	31		T3	51
valid_sources[0x2d]	31206	1			T1	9		T2	44		T3	65
valid_sources[0x2e]	32718	1			T1	18		T2	65		T3	44
valid_sources[0x2f]	29220	1			T1	20		T2	56		T3	53
valid_sources[0x30]	26626	1			T1	16		T2	24		T3	53
valid_sources[0x31]	40408	1			T1	26		T2	33		T3	63
valid_sources[0x32]	30003	1			T1	19		T2	34		T3	57
valid_sources[0x33]	31713	1			T1	21		T2	37		T3	38
valid_sources[0x34]	33681	1			T1	2		T2	50		T3	43
valid_sources[0x35]	28714	1			T1	21		T2	23		T3	35
valid_sources[0x36]	29683	1			T1	14		T2	37		T3	42
valid_sources[0x37]	29881	1			T1	8		T2	46		T3	46
valid_sources[0x38]	31709	1			T1	9		T2	34		T3	53
valid_sources[0x39]	31138	1			T1	13		T2	41		T3	63
valid_sources[0x3a]	29010	1			T1	10		T2	38		T3	46
valid_sources[0x3b]	27220	1			T1	20		T2	43		T3	50
valid_sources[0x3c]	27457	1			T1	11		T2	45		T3	41
valid_sources[0x3d]	27618	1			T1	37		T2	53		T3	66
valid_sources[0x3e]	29614	1			T1	12		T2	23		T3	43
valid_sources[0x3f]	26957	1			T1	7		T2	44		T3	65
valid_sources[0x40]	34251	1			T1	15		T2	15		T3	45
valid_sources[0x41]	30924	1			T1	25		T2	67		T3	54
valid_sources[0x42]	31749	1			T1	10		T2	71		T3	51
valid_sources[0x43]	28044	1			T1	24		T2	21		T3	44
valid_sources[0x44]	28117	1			T1	27		T2	18		T3	42
valid_sources[0x45]	26919	1			T1	17		T2	27		T3	42
valid_sources[0x46]	28599	1			T1	12		T2	24		T3	42
valid_sources[0x47]	27800	1			T1	6		T2	55		T3	73
valid_sources[0x48]	28167	1			T1	23		T2	24		T3	46
valid_sources[0x49]	32138	1			T1	47		T2	56		T3	36
valid_sources[0x4a]	31522	1			T1	3		T2	15		T3	49
valid_sources[0x4b]	30760	1			T1	6		T2	47		T3	54
valid_sources[0x4c]	30142	1			T1	36		T2	27		T3	51
valid_sources[0x4d]	27825	1			T1	8		T2	42		T3	46
valid_sources[0x4e]	30831	1			T1	1		T2	17		T3	57
valid_sources[0x4f]	29334	1			T1	21		T2	30		T3	42
valid_sources[0x50]	30869	1			T1	25		T2	36		T3	54
valid_sources[0x51]	34138	1			T1	10		T2	30		T3	44
valid_sources[0x52]	30360	1			T1	29		T2	27		T3	56
valid_sources[0x53]	30461	1			T1	8		T2	21		T3	50
valid_sources[0x54]	29843	1			T1	32		T2	26		T3	60
valid_sources[0x55]	29053	1			T1	10		T2	30		T3	47
valid_sources[0x56]	27820	1			T1	16		T2	37		T3	57
valid_sources[0x57]	29553	1			T1	10		T2	41		T3	53
valid_sources[0x58]	37557	1			T1	46		T2	25		T3	61
valid_sources[0x59]	31804	1			T1	48		T2	19		T3	53
valid_sources[0x5a]	35882	1			T1	11		T2	26		T3	49
valid_sources[0x5b]	27874	1			T1	16		T2	34		T3	66
valid_sources[0x5c]	27914	1			T1	8		T2	32		T3	56
valid_sources[0x5d]	30538	1			T1	12		T2	19		T3	58
valid_sources[0x5e]	32757	1			T1	20		T2	43		T3	52
valid_sources[0x5f]	28775	1			T1	32		T2	37		T3	44
valid_sources[0x60]	28913	1			T1	13		T2	34		T3	56
valid_sources[0x61]	29500	1			T1	16		T2	70		T3	51
valid_sources[0x62]	29731	1			T1	1		T2	24		T3	49
valid_sources[0x63]	32077	1			T1	19		T2	25		T3	55
valid_sources[0x64]	29624	1			T1	19		T2	18		T3	53
valid_sources[0x65]	27774	1			T1	1		T2	43		T3	49
valid_sources[0x66]	26677	1			T1	5		T2	42		T3	44
valid_sources[0x67]	31030	1			T1	30		T2	18		T3	51
valid_sources[0x68]	29045	1			T1	12		T2	28		T3	45
valid_sources[0x69]	30159	1			T1	13		T2	40		T3	57
valid_sources[0x6a]	30063	1			T1	27		T2	34		T3	57
valid_sources[0x6b]	29260	1			T1	7		T2	28		T3	54
valid_sources[0x6c]	28821	1			T1	11		T2	40		T3	67
valid_sources[0x6d]	30275	1			T1	22		T2	15		T3	50
valid_sources[0x6e]	27812	1			T1	37		T2	28		T3	53
valid_sources[0x6f]	28201	1			T1	1		T2	25		T3	56
valid_sources[0x70]	28609	1			T1	10		T2	51		T3	44
valid_sources[0x71]	31427	1			T1	30		T2	17		T3	56
valid_sources[0x72]	26725	1			T1	14		T2	51		T3	47
valid_sources[0x73]	28456	1			T1	8		T2	47		T3	49
valid_sources[0x74]	30101	1			T1	39		T2	17		T3	50
valid_sources[0x75]	27603	1			T2	33		T3	45		T5	36
valid_sources[0x76]	28263	1			T1	16		T2	20		T3	44
valid_sources[0x77]	33583	1			T1	12		T2	23		T3	57
valid_sources[0x78]	29610	1			T1	27		T2	28		T3	53
valid_sources[0x79]	28493	1			T1	46		T2	35		T3	56
valid_sources[0x7a]	27087	1			T1	45		T2	33		T3	60
valid_sources[0x7b]	30184	1			T1	13		T2	23		T3	68
valid_sources[0x7c]	31254	1			T1	11		T2	40		T3	57
valid_sources[0x7d]	28295	1			T1	2		T2	22		T3	45
valid_sources[0x7e]	30389	1			T1	14		T2	34		T3	51
valid_sources[0x7f]	29403	1			T1	7		T2	24		T3	51
valid_sources[0x80]	27800	1			T1	12		T2	48		T3	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1099545

1

T1

1696

T2

1188

T3

6266

values[0x0]

all_enables

biggest_size

1577793

1

T1

436

T2

3128

T3

442

values[0x1]

all_enables

biggest_size

1555471

1

T1

461

T2

2993

T3

450