Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3497130

1

T1

1785

T2

1188

T3

6173

full_word

4231981

1

T1

2593

T2

7309

T3

7158

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7728731	1			T1	4378		T2	8497		T3	13331
auto[TlIntgErrCmd]	135	1			T97	3		T98	8		T100	10
auto[TlIntgErrData]	111	1			T97	2		T98	6		T100	3
auto[TlIntgErrBoth]	134	1			T97	5		T98	6		T100	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4261303

1

T1

3475

T2

2341

T3

12434

auto[1]

3467808

1

T1

903

T2

6156

T3

897

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3161507	1			T1	1779		T2	1153		T3	6168
auto[TlIntgErrNone]	partial	auto[1]	335280	1			T1	6		T2	35		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1099628	1			T1	1696		T2	1188		T3	6266
auto[TlIntgErrNone]	full_word	auto[1]	3132316	1			T1	897		T2	6121		T3	892
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T97	1		T98	3		T100	5
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T97	1		T98	5		T100	4
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T100	1		T110	1		T107	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T97	1		T157	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T97	1		T98	4		T100	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T97	1		T98	2		T100	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T110	1		T158	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T100	1		T110	1		T107	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T97	2		T98	4		T100	2
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T97	3		T98	2		T100	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T100	1		T157	1		T159	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T107	1		T108	1		T109	1