Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505358314	2901265	0	0
DepthKnown_A	505358314	505228026	0	0
RvalidKnown_A	505358314	505228026	0	0
WreadyKnown_A	505358314	505228026	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	2901265	0	0
T1	125217	1663	0	0
T2	150097	7494	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	1663	0	0
T6	118814	14972	0	0
T7	146080	8325	0	0
T8	6867	832	0	0
T9	170968	1663	0	0
T10	16810	832	0	0
T11	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505358314	3128198	0	0
DepthKnown_A	505358314	505228026	0	0
RvalidKnown_A	505358314	505228026	0	0
WreadyKnown_A	505358314	505228026	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	3128198	0	0
T1	125217	832	0	0
T2	150097	17547	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	11648	0	0
T7	146080	17220	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	2623	0	0
T11	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505358314	192599	0	0
DepthKnown_A	505358314	505228026	0	0
RvalidKnown_A	505358314	505228026	0	0
WreadyKnown_A	505358314	505228026	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	192599	0	0
T2	150097	128	0	0
T3	258300	0	0	0
T4	6298	0	0	0
T5	269286	0	0	0
T6	118814	1043	0	0
T7	146080	75	0	0
T8	6867	0	0	0
T9	170968	0	0	0
T10	16810	0	0	0
T11	175868	0	0	0
T28	0	920	0	0
T30	0	25	0	0
T31	0	817	0	0
T33	0	1135	0	0
T40	0	416	0	0
T41	0	64	0	0
T42	0	704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505358314	421110	0	0
DepthKnown_A	505358314	505228026	0	0
RvalidKnown_A	505358314	505228026	0	0
WreadyKnown_A	505358314	505228026	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	421110	0	0
T2	150097	578	0	0
T3	258300	0	0	0
T4	6298	0	0	0
T5	269286	0	0	0
T6	118814	1043	0	0
T7	146080	270	0	0
T8	6867	0	0	0
T9	170968	0	0	0
T10	16810	0	0	0
T11	175868	0	0	0
T28	0	920	0	0
T30	0	25	0	0
T31	0	817	0	0
T33	0	5038	0	0
T40	0	416	0	0
T41	0	64	0	0
T42	0	704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505358314	6024060	0	0
DepthKnown_A	505358314	505228026	0	0
RvalidKnown_A	505358314	505228026	0	0
WreadyKnown_A	505358314	505228026	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	6024060	0	0
T1	125217	3557	0	0
T2	150097	2565	0	0
T3	258300	12499	0	0
T4	6298	35	0	0
T5	269286	10838	0	0
T6	118814	12836	0	0
T7	146080	1039	0	0
T8	6867	300	0	0
T9	170968	8280	0	0
T10	16810	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505358314	12629960	0	0
DepthKnown_A	505358314	505228026	0	0
RvalidKnown_A	505358314	505228026	0	0
WreadyKnown_A	505358314	505228026	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	12629960	0	0
T1	125217	15248	0	0
T2	150097	10061	0	0
T3	258300	12499	0	0
T4	6298	35	0	0
T5	269286	46761	0	0
T6	118814	12750	0	0
T7	146080	3185	0	0
T8	6867	298	0	0
T9	170968	8280	0	0
T10	16810	251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505358314	505228026	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0