Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T28,T30
1	0	Covered	T6,T28,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T25
1	0	Unreachable
1	1	Covered	T6,T28,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	802718549	651452729	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	802718549	3766660	0	0
GntImpliesValid_A	802718549	3766660	0	0
GrantKnown_A	802718549	651452729	0	0
IdxKnown_A	802718549	651452729	0	0
IndexIsCorrect_A	802718549	3766660	0	0
LockArbDecision_A	802718549	0	0	0
NoReadyValidNoGrant_A	802718549	0	0	0
ReadyAndValidImplyGrant_A	802718549	3766660	0	0
ReqAndReadyImplyGrant_A	802718549	3766660	0	0
ReqImpliesValid_A	802718549	3766660	0	0
ReqStaysHighUntilGranted0_M	802718549	0	0	0
RoundRobin_A	802718549	6	0	974
ValidKnown_A	802718549	651452729	0	0
gen_data_port_assertion.DataFlow_A	802718549	3766660	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	651452729	0	0
T1	149538	149074	0	0
T2	633173	631323	0	0
T3	321146	320705	0	0
T4	8574	7034	0	0
T5	356704	312067	0	0
T6	1596450	853273	0	0
T7	646588	394098	0	0
T8	37119	21910	0	0
T9	212824	191815	0	0
T10	42294	29493	0	0
T11	172844	172844	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	3766660	0	0
T1	125217	832	0	0
T2	633173	9030	0	0
T3	321146	832	0	0
T4	7436	0	0	0
T5	312995	832	0	0
T6	1596450	27927	0	0
T7	646588	7050	0	0
T8	37119	832	0	0
T9	212824	832	0	0
T10	42294	832	0	0
T11	345688	832	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	6465	0	0
T33	0	7650	0	0
T34	0	4868	0	0
T40	0	8964	0	0
T49	74348	2	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	3766660	0	0
T1	125217	832	0	0
T2	633173	9030	0	0
T3	321146	832	0	0
T4	7436	0	0	0
T5	312995	832	0	0
T6	1596450	27927	0	0
T7	646588	7050	0	0
T8	37119	832	0	0
T9	212824	832	0	0
T10	42294	832	0	0
T11	345688	832	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	6465	0	0
T33	0	7650	0	0
T34	0	4868	0	0
T40	0	8964	0	0
T49	74348	2	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	651452729	0	0
T1	149538	149074	0	0
T2	633173	631323	0	0
T3	321146	320705	0	0
T4	8574	7034	0	0
T5	356704	312067	0	0
T6	1596450	853273	0	0
T7	646588	394098	0	0
T8	37119	21910	0	0
T9	212824	191815	0	0
T10	42294	29493	0	0
T11	172844	172844	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	651452729	0	0
T1	149538	149074	0	0
T2	633173	631323	0	0
T3	321146	320705	0	0
T4	8574	7034	0	0
T5	356704	312067	0	0
T6	1596450	853273	0	0
T7	646588	394098	0	0
T8	37119	21910	0	0
T9	212824	191815	0	0
T10	42294	29493	0	0
T11	172844	172844	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	3766660	0	0
T1	125217	832	0	0
T2	633173	9030	0	0
T3	321146	832	0	0
T4	7436	0	0	0
T5	312995	832	0	0
T6	1596450	27927	0	0
T7	646588	7050	0	0
T8	37119	832	0	0
T9	212824	832	0	0
T10	42294	832	0	0
T11	345688	832	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	6465	0	0
T33	0	7650	0	0
T34	0	4868	0	0
T40	0	8964	0	0
T49	74348	2	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	3766660	0	0
T1	125217	832	0	0
T2	633173	9030	0	0
T3	321146	832	0	0
T4	7436	0	0	0
T5	312995	832	0	0
T6	1596450	27927	0	0
T7	646588	7050	0	0
T8	37119	832	0	0
T9	212824	832	0	0
T10	42294	832	0	0
T11	345688	832	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	6465	0	0
T33	0	7650	0	0
T34	0	4868	0	0
T40	0	8964	0	0
T49	74348	2	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	3766660	0	0
T1	125217	832	0	0
T2	633173	9030	0	0
T3	321146	832	0	0
T4	7436	0	0	0
T5	312995	832	0	0
T6	1596450	27927	0	0
T7	646588	7050	0	0
T8	37119	832	0	0
T9	212824	832	0	0
T10	42294	832	0	0
T11	345688	832	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	6465	0	0
T33	0	7650	0	0
T34	0	4868	0	0
T40	0	8964	0	0
T49	74348	2	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	3766660	0	0
T1	125217	832	0	0
T2	633173	9030	0	0
T3	321146	832	0	0
T4	7436	0	0	0
T5	312995	832	0	0
T6	1596450	27927	0	0
T7	646588	7050	0	0
T8	37119	832	0	0
T9	212824	832	0	0
T10	42294	832	0	0
T11	345688	832	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	6465	0	0
T33	0	7650	0	0
T34	0	4868	0	0
T40	0	8964	0	0
T49	74348	2	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	6	0	974
T34	245125	1	0	1
T47	59277	0	0	1
T56	208619	0	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	1761	0	0	1
T65	106198	0	0	1
T66	4433	0	0	1
T67	59190	0	0	1
T68	18317	0	0	1
T69	5904	0	0	1
T70	331380	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	651452729	0	0
T1	149538	149074	0	0
T2	633173	631323	0	0
T3	321146	320705	0	0
T4	8574	7034	0	0
T5	356704	312067	0	0
T6	1596450	853273	0	0
T7	646588	394098	0	0
T8	37119	21910	0	0
T9	212824	191815	0	0
T10	42294	29493	0	0
T11	172844	172844	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802718549	3766660	0	0
T1	125217	832	0	0
T2	633173	9030	0	0
T3	321146	832	0	0
T4	7436	0	0	0
T5	312995	832	0	0
T6	1596450	27927	0	0
T7	646588	7050	0	0
T8	37119	832	0	0
T9	212824	832	0	0
T10	42294	832	0	0
T11	345688	832	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	6465	0	0
T33	0	7650	0	0
T34	0	4868	0	0
T40	0	8964	0	0
T49	74348	2	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T28,T30
1	0	Covered	T6,T28,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T25
1	0	Unreachable
1	1	Covered	T6,T28,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T28,T30
0	0	1	Unreachable
0	0	0	Covered	T4,T6,T25

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T28,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T28,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149839539	26919301	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	149839539	648171	0	0
GntImpliesValid_A	149839539	648171	0	0
GrantKnown_A	149839539	26919301	0	0
IdxKnown_A	149839539	26919301	0	0
IndexIsCorrect_A	149839539	648171	0	0
LockArbDecision_A	149839539	0	0	0
NoReadyValidNoGrant_A	149839539	0	0	0
ReadyAndValidImplyGrant_A	149839539	648171	0	0
ReqAndReadyImplyGrant_A	149839539	648171	0	0
ReqImpliesValid_A	149839539	648171	0	0
ReqStaysHighUntilGranted0_M	149839539	0	0	0
RoundRobin_A	149839539	0	0	0
ValidKnown_A	149839539	26919301	0	0
gen_data_port_assertion.DataFlow_A	149839539	648171	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	26919301	0	0
T4	1138	792	0	0
T5	43709	0	0	0
T6	738818	68280	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	648171	0	0
T6	738818	2025	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	4231	0	0
T33	0	4458	0	0
T34	0	4868	0	0
T49	74348	0	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	648171	0	0
T6	738818	2025	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	4231	0	0
T33	0	4458	0	0
T34	0	4868	0	0
T49	74348	0	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	26919301	0	0
T4	1138	792	0	0
T5	43709	0	0	0
T6	738818	68280	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	26919301	0	0
T4	1138	792	0	0
T5	43709	0	0	0
T6	738818	68280	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	648171	0	0
T6	738818	2025	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	4231	0	0
T33	0	4458	0	0
T34	0	4868	0	0
T49	74348	0	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	648171	0	0
T6	738818	2025	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	4231	0	0
T33	0	4458	0	0
T34	0	4868	0	0
T49	74348	0	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	648171	0	0
T6	738818	2025	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	4231	0	0
T33	0	4458	0	0
T34	0	4868	0	0
T49	74348	0	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	648171	0	0
T6	738818	2025	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	4231	0	0
T33	0	4458	0	0
T34	0	4868	0	0
T49	74348	0	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	26919301	0	0
T4	1138	792	0	0
T5	43709	0	0	0
T6	738818	68280	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T25	0	93536	0	0
T26	0	72	0	0
T27	0	36264	0	0
T28	0	111832	0	0
T29	0	44120	0	0
T30	0	3184	0	0
T31	0	157408	0	0
T32	0	111616	0	0
T49	74348	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	648171	0	0
T6	738818	2025	0	0
T7	250254	0	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T22	54786	0	0	0
T28	0	5252	0	0
T30	0	153	0	0
T31	0	4231	0	0
T33	0	4458	0	0
T34	0	4868	0	0
T49	74348	0	0	0
T52	0	1354	0	0
T54	15746	0	0	0
T55	134720	0	0	0
T56	0	3344	0	0
T57	0	342	0	0
T58	0	2207	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149839539	121581292	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	149839539	830042	0	0
GntImpliesValid_A	149839539	830042	0	0
GrantKnown_A	149839539	121581292	0	0
IdxKnown_A	149839539	121581292	0	0
IndexIsCorrect_A	149839539	830042	0	0
LockArbDecision_A	149839539	0	0	0
NoReadyValidNoGrant_A	149839539	0	0	0
ReadyAndValidImplyGrant_A	149839539	830042	0	0
ReqAndReadyImplyGrant_A	149839539	830042	0	0
ReqImpliesValid_A	149839539	830042	0	0
ReqStaysHighUntilGranted0_M	149839539	0	0	0
RoundRobin_A	149839539	0	0	0
ValidKnown_A	149839539	121581292	0	0
gen_data_port_assertion.DataFlow_A	149839539	830042	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	121581292	0	0
T1	24321	23908	0	0
T2	483076	481233	0	0
T3	62846	62496	0	0
T4	1138	0	0	0
T5	43709	42876	0	0
T6	738818	666214	0	0
T7	250254	248107	0	0
T8	15126	15126	0	0
T9	20928	20928	0	0
T10	12742	12742	0	0
T11	0	172844	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	830042	0	0
T2	483076	3070	0	0
T3	62846	0	0	0
T4	1138	0	0	0
T5	43709	0	0	0
T6	738818	12522	0	0
T7	250254	311	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T31	0	2234	0	0
T33	0	3192	0	0
T40	0	8964	0	0
T41	0	271	0	0
T42	0	7781	0	0
T49	0	2	0	0
T71	0	6000	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	830042	0	0
T2	483076	3070	0	0
T3	62846	0	0	0
T4	1138	0	0	0
T5	43709	0	0	0
T6	738818	12522	0	0
T7	250254	311	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T31	0	2234	0	0
T33	0	3192	0	0
T40	0	8964	0	0
T41	0	271	0	0
T42	0	7781	0	0
T49	0	2	0	0
T71	0	6000	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	121581292	0	0
T1	24321	23908	0	0
T2	483076	481233	0	0
T3	62846	62496	0	0
T4	1138	0	0	0
T5	43709	42876	0	0
T6	738818	666214	0	0
T7	250254	248107	0	0
T8	15126	15126	0	0
T9	20928	20928	0	0
T10	12742	12742	0	0
T11	0	172844	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	121581292	0	0
T1	24321	23908	0	0
T2	483076	481233	0	0
T3	62846	62496	0	0
T4	1138	0	0	0
T5	43709	42876	0	0
T6	738818	666214	0	0
T7	250254	248107	0	0
T8	15126	15126	0	0
T9	20928	20928	0	0
T10	12742	12742	0	0
T11	0	172844	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	830042	0	0
T2	483076	3070	0	0
T3	62846	0	0	0
T4	1138	0	0	0
T5	43709	0	0	0
T6	738818	12522	0	0
T7	250254	311	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T31	0	2234	0	0
T33	0	3192	0	0
T40	0	8964	0	0
T41	0	271	0	0
T42	0	7781	0	0
T49	0	2	0	0
T71	0	6000	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	830042	0	0
T2	483076	3070	0	0
T3	62846	0	0	0
T4	1138	0	0	0
T5	43709	0	0	0
T6	738818	12522	0	0
T7	250254	311	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T31	0	2234	0	0
T33	0	3192	0	0
T40	0	8964	0	0
T41	0	271	0	0
T42	0	7781	0	0
T49	0	2	0	0
T71	0	6000	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	830042	0	0
T2	483076	3070	0	0
T3	62846	0	0	0
T4	1138	0	0	0
T5	43709	0	0	0
T6	738818	12522	0	0
T7	250254	311	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T31	0	2234	0	0
T33	0	3192	0	0
T40	0	8964	0	0
T41	0	271	0	0
T42	0	7781	0	0
T49	0	2	0	0
T71	0	6000	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	830042	0	0
T2	483076	3070	0	0
T3	62846	0	0	0
T4	1138	0	0	0
T5	43709	0	0	0
T6	738818	12522	0	0
T7	250254	311	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T31	0	2234	0	0
T33	0	3192	0	0
T40	0	8964	0	0
T41	0	271	0	0
T42	0	7781	0	0
T49	0	2	0	0
T71	0	6000	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	121581292	0	0
T1	24321	23908	0	0
T2	483076	481233	0	0
T3	62846	62496	0	0
T4	1138	0	0	0
T5	43709	42876	0	0
T6	738818	666214	0	0
T7	250254	248107	0	0
T8	15126	15126	0	0
T9	20928	20928	0	0
T10	12742	12742	0	0
T11	0	172844	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149839539	830042	0	0
T2	483076	3070	0	0
T3	62846	0	0	0
T4	1138	0	0	0
T5	43709	0	0	0
T6	738818	12522	0	0
T7	250254	311	0	0
T8	15126	0	0	0
T9	20928	0	0	0
T10	12742	0	0	0
T11	172844	0	0	0
T31	0	2234	0	0
T33	0	3192	0	0
T40	0	8964	0	0
T41	0	271	0	0
T42	0	7781	0	0
T49	0	2	0	0
T71	0	6000	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	503039471	502952136	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	503039471	2288447	0	0
GntImpliesValid_A	503039471	2288447	0	0
GrantKnown_A	503039471	502952136	0	0
IdxKnown_A	503039471	502952136	0	0
IndexIsCorrect_A	503039471	2288447	0	0
LockArbDecision_A	503039471	0	0	0
NoReadyValidNoGrant_A	503039471	0	0	0
ReadyAndValidImplyGrant_A	503039471	2288447	0	0
ReqAndReadyImplyGrant_A	503039471	2288447	0	0
ReqImpliesValid_A	503039471	2288447	0	0
ReqStaysHighUntilGranted0_M	503039471	0	0	0
RoundRobin_A	503039471	6	0	974
ValidKnown_A	503039471	502952136	0	0
gen_data_port_assertion.DataFlow_A	503039471	2288447	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	502952136	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	2288447	0	0
T1	125217	832	0	0
T2	150097	5960	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	13380	0	0
T7	146080	6739	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	832	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	2288447	0	0
T1	125217	832	0	0
T2	150097	5960	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	13380	0	0
T7	146080	6739	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	832	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	502952136	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	502952136	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	2288447	0	0
T1	125217	832	0	0
T2	150097	5960	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	13380	0	0
T7	146080	6739	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	832	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	2288447	0	0
T1	125217	832	0	0
T2	150097	5960	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	13380	0	0
T7	146080	6739	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	832	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	2288447	0	0
T1	125217	832	0	0
T2	150097	5960	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	13380	0	0
T7	146080	6739	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	832	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	2288447	0	0
T1	125217	832	0	0
T2	150097	5960	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	13380	0	0
T7	146080	6739	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	832	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	6	0	974
T34	245125	1	0	1
T47	59277	0	0	1
T56	208619	0	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	1761	0	0	1
T65	106198	0	0	1
T66	4433	0	0	1
T67	59190	0	0	1
T68	18317	0	0	1
T69	5904	0	0	1
T70	331380	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	502952136	0	0
T1	125217	125166	0	0
T2	150097	150090	0	0
T3	258300	258209	0	0
T4	6298	6242	0	0
T5	269286	269191	0	0
T6	118814	118779	0	0
T7	146080	145991	0	0
T8	6867	6784	0	0
T9	170968	170887	0	0
T10	16810	16751	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503039471	2288447	0	0
T1	125217	832	0	0
T2	150097	5960	0	0
T3	258300	832	0	0
T4	6298	0	0	0
T5	269286	832	0	0
T6	118814	13380	0	0
T7	146080	6739	0	0
T8	6867	832	0	0
T9	170968	832	0	0
T10	16810	832	0	0
T11	0	832	0	0