Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3853445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4427905

1

T1

1042

T2

2836

T3

881

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4563740	1			T1	302		T2	347		T3	3
values[0x0]	1858117	1			T1	447		T2	1312		T3	475
values[0x1]	1859493	1			T1	445		T2	1332		T3	407

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2727346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5554004

1

T1

1071

T2

2865

T3

882

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32552	1			T4	6		T7	1		T9	52
valid_sources[0x01]	30254	1			T1	26		T4	5		T7	115
valid_sources[0x02]	31555	1			T1	10		T4	4		T9	71
valid_sources[0x03]	35574	1			T4	2		T9	73		T10	25
valid_sources[0x04]	36840	1			T4	5		T9	60		T10	22
valid_sources[0x05]	31962	1			T1	11		T4	2		T9	73
valid_sources[0x06]	29291	1			T4	2		T9	68		T10	13
valid_sources[0x07]	33313	1			T2	1		T4	3		T7	273
valid_sources[0x08]	29695	1			T4	2		T9	69		T10	23
valid_sources[0x09]	31360	1			T1	1		T4	3		T9	56
valid_sources[0x0a]	37247	1			T1	43		T4	6		T7	1
valid_sources[0x0b]	30730	1			T1	27		T9	67		T10	23
valid_sources[0x0c]	29788	1			T1	8		T7	1		T9	59
valid_sources[0x0d]	30352	1			T4	3		T9	48		T10	31
valid_sources[0x0e]	30983	1			T2	1		T4	4		T9	58
valid_sources[0x0f]	32222	1			T1	15		T4	5		T9	39
valid_sources[0x10]	38353	1			T1	16		T4	3		T9	67
valid_sources[0x11]	31306	1			T4	1		T9	62		T10	21
valid_sources[0x12]	29492	1			T1	2		T4	2		T9	51
valid_sources[0x13]	30028	1			T4	3		T9	57		T10	24
valid_sources[0x14]	30297	1			T4	4		T7	1		T9	72
valid_sources[0x15]	31603	1			T4	2		T9	55		T10	21
valid_sources[0x16]	33028	1			T1	38		T4	4		T5	5
valid_sources[0x17]	30153	1			T4	1		T9	51		T10	28
valid_sources[0x18]	33058	1			T1	1		T4	4		T9	55
valid_sources[0x19]	40794	1			T4	2		T7	1		T9	65
valid_sources[0x1a]	32463	1			T4	3		T9	68		T10	35
valid_sources[0x1b]	35034	1			T1	10		T4	4		T9	59
valid_sources[0x1c]	32406	1			T1	6		T4	4		T9	65
valid_sources[0x1d]	32321	1			T1	12		T4	3		T5	1
valid_sources[0x1e]	46005	1			T4	3		T9	55		T10	25
valid_sources[0x1f]	34473	1			T1	3		T4	4		T7	1
valid_sources[0x20]	32270	1			T4	4		T9	53		T10	29
valid_sources[0x21]	33264	1			T4	3		T9	67		T10	25
valid_sources[0x22]	30019	1			T4	8		T9	47		T10	35
valid_sources[0x23]	29528	1			T1	7		T4	2		T7	141
valid_sources[0x24]	30117	1			T1	7		T4	4		T5	3
valid_sources[0x25]	29615	1			T4	6		T9	62		T10	23
valid_sources[0x26]	29088	1			T1	2		T4	6		T9	60
valid_sources[0x27]	31163	1			T4	3		T5	8		T9	60
valid_sources[0x28]	32624	1			T1	15		T4	7		T5	2
valid_sources[0x29]	32252	1			T4	1		T9	65		T10	31
valid_sources[0x2a]	33889	1			T4	3		T7	1		T9	40
valid_sources[0x2b]	30502	1			T4	3		T9	78		T10	26
valid_sources[0x2c]	48598	1			T4	2		T7	306		T9	64
valid_sources[0x2d]	30608	1			T4	1		T9	59		T10	32
valid_sources[0x2e]	35637	1			T1	5		T4	5		T9	69
valid_sources[0x2f]	32588	1			T4	5		T9	71		T10	19
valid_sources[0x30]	29321	1			T2	1		T4	2		T7	1
valid_sources[0x31]	32758	1			T4	5		T9	60		T10	21
valid_sources[0x32]	31007	1			T4	3		T9	53		T10	24
valid_sources[0x33]	31110	1			T1	7		T2	1		T4	6
valid_sources[0x34]	30648	1			T1	9		T4	6		T9	58
valid_sources[0x35]	30200	1			T1	1		T4	4		T9	57
valid_sources[0x36]	31220	1			T1	23		T4	3		T9	64
valid_sources[0x37]	32177	1			T4	4		T9	59		T10	20
valid_sources[0x38]	34632	1			T4	4		T5	1		T9	78
valid_sources[0x39]	31474	1			T2	104		T4	5		T9	67
valid_sources[0x3a]	34453	1			T1	4		T4	2		T9	65
valid_sources[0x3b]	31614	1			T4	3		T9	55		T10	19
valid_sources[0x3c]	35950	1			T1	4		T4	4		T9	46
valid_sources[0x3d]	35806	1			T4	6		T9	59		T10	23
valid_sources[0x3e]	32059	1			T4	3		T9	61		T10	21
valid_sources[0x3f]	32621	1			T4	2		T9	55		T10	24
valid_sources[0x40]	33998	1			T4	4		T7	1009		T9	62
valid_sources[0x41]	31517	1			T4	2		T9	62		T10	31
valid_sources[0x42]	31511	1			T4	4		T5	1		T7	1458
valid_sources[0x43]	31412	1			T4	5		T9	67		T10	22
valid_sources[0x44]	29935	1			T2	1		T4	3		T9	53
valid_sources[0x45]	32739	1			T1	10		T4	2		T9	61
valid_sources[0x46]	33796	1			T2	1		T4	5		T9	56
valid_sources[0x47]	31940	1			T1	17		T4	3		T9	58
valid_sources[0x48]	38705	1			T4	4		T9	70		T10	18
valid_sources[0x49]	32795	1			T2	2		T4	1		T9	70
valid_sources[0x4a]	34531	1			T1	2		T4	3		T9	52
valid_sources[0x4b]	29254	1			T1	1		T4	11		T9	59
valid_sources[0x4c]	36668	1			T1	5		T4	4		T7	1
valid_sources[0x4d]	29482	1			T1	5		T4	3		T9	59
valid_sources[0x4e]	30735	1			T4	3		T9	48		T10	21
valid_sources[0x4f]	31214	1			T4	1		T9	55		T10	22
valid_sources[0x50]	29101	1			T3	451		T4	3		T9	54
valid_sources[0x51]	40146	1			T1	1		T4	2		T7	1
valid_sources[0x52]	29800	1			T1	36		T4	1		T9	52
valid_sources[0x53]	36067	1			T4	3		T9	61		T10	19
valid_sources[0x54]	31662	1			T4	5		T5	3		T9	60
valid_sources[0x55]	29388	1			T1	15		T4	4		T5	2
valid_sources[0x56]	33429	1			T1	9		T4	2		T9	59
valid_sources[0x57]	30760	1			T4	10		T7	1		T9	59
valid_sources[0x58]	32699	1			T1	1		T4	1		T9	67
valid_sources[0x59]	31427	1			T1	10		T4	2		T9	64
valid_sources[0x5a]	38444	1			T4	5		T9	67		T10	23
valid_sources[0x5b]	35605	1			T1	8		T4	5		T9	57
valid_sources[0x5c]	29829	1			T4	3		T9	63		T10	28
valid_sources[0x5d]	30836	1			T1	20		T4	1		T9	77
valid_sources[0x5e]	31622	1			T1	2		T4	6		T5	8
valid_sources[0x5f]	30629	1			T1	2		T4	3		T7	1
valid_sources[0x60]	34616	1			T4	1		T9	72		T10	21
valid_sources[0x61]	45719	1			T1	4		T4	3		T9	53
valid_sources[0x62]	28968	1			T9	62		T10	28		T24	7
valid_sources[0x63]	30553	1			T4	2		T9	65		T10	22
valid_sources[0x64]	36576	1			T1	14		T4	4		T7	416
valid_sources[0x65]	31585	1			T4	3		T7	1		T9	65
valid_sources[0x66]	31433	1			T4	5		T9	76		T10	18
valid_sources[0x67]	31223	1			T4	4		T7	1		T9	58
valid_sources[0x68]	29742	1			T1	4		T4	6		T9	53
valid_sources[0x69]	30495	1			T4	3		T9	71		T10	32
valid_sources[0x6a]	29979	1			T1	2		T4	1		T9	71
valid_sources[0x6b]	32543	1			T4	2		T9	47		T10	27
valid_sources[0x6c]	34668	1			T1	9		T4	1		T9	69
valid_sources[0x6d]	30683	1			T1	7		T4	5		T9	62
valid_sources[0x6e]	30040	1			T4	2		T9	49		T10	28
valid_sources[0x6f]	36037	1			T1	4		T4	4		T9	55
valid_sources[0x70]	30376	1			T1	1		T4	2		T5	1
valid_sources[0x71]	28164	1			T4	3		T9	61		T10	24
valid_sources[0x72]	30259	1			T1	12		T4	5		T7	1
valid_sources[0x73]	31757	1			T1	14		T4	7		T9	57
valid_sources[0x74]	29066	1			T4	6		T9	53		T10	21
valid_sources[0x75]	31050	1			T4	3		T5	2		T7	24
valid_sources[0x76]	31052	1			T1	1		T2	1		T4	3
valid_sources[0x77]	29859	1			T4	8		T7	1		T9	64
valid_sources[0x78]	32778	1			T4	10		T9	59		T10	27
valid_sources[0x79]	34549	1			T4	3		T9	69		T10	23
valid_sources[0x7a]	29951	1			T1	2		T4	3		T9	54
valid_sources[0x7b]	30436	1			T1	19		T4	4		T7	3
valid_sources[0x7c]	33318	1			T4	3		T7	2050		T9	70
valid_sources[0x7d]	32906	1			T4	4		T9	68		T10	19
valid_sources[0x7e]	31647	1			T4	4		T7	1		T9	65
valid_sources[0x7f]	32361	1			T4	1		T9	54		T10	34
valid_sources[0x80]	39065	1			T4	2		T5	3		T7	2961

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1064600

1

T1

154

T2

209

T4

9

values[0x0]

all_enables

biggest_size

1694225

1

T1

445

T2

1309

T3

474

values[0x1]

all_enables

biggest_size

1669080

1

T1

443

T2

1318

T3

407