Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3874267

1

T1

152

T2

155

T3

4

full_word

4426924

1

T1

1042

T2

2836

T3

881

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8300771	1			T1	1194		T2	2991		T3	885
auto[TlIntgErrCmd]	152	1			T99	11		T100	7		T101	6
auto[TlIntgErrData]	136	1			T99	10		T100	2		T101	8
auto[TlIntgErrBoth]	132	1			T99	9		T100	1		T101	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4565329

1

T1

302

T2

347

T3

3

auto[1]

3735862

1

T1

892

T2

2644

T3

882

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3500454	1			T1	148		T2	138		T3	3
auto[TlIntgErrNone]	partial	auto[1]	373425	1			T1	4		T2	17		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	1064674	1			T1	154		T2	209		T4	9
auto[TlIntgErrNone]	full_word	auto[1]	3362218	1			T1	888		T2	2627		T3	881
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T99	4		T100	5		T101	4
auto[TlIntgErrCmd]	partial	auto[1]	82	1			T99	7		T100	2		T101	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T237	1		T152	1		T238	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T152	1		T154	2		T239	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T99	6		T100	2		T101	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T99	2		T101	4		T236	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T99	1		T101	1		T154	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T99	1		T154	1		T240	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T99	2		T101	2		T236	4
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T99	7		T100	1		T101	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T152	1		T241	1		T240	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T101	1		T152	2		T242	1