Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488287515	2985217	0	0
DepthKnown_A	488287515	488150183	0	0
RvalidKnown_A	488287515	488150183	0	0
WreadyKnown_A	488287515	488150183	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	2985217	0	0
T1	242750	1663	0	0
T2	154066	3328	0	0
T3	70650	1668	0	0
T4	3260	1663	0	0
T5	1326	0	0	0
T6	4752	1663	0	0
T7	291198	14970	0	0
T8	96272	832	0	0
T9	275077	9148	0	0
T10	123063	1663	0	0
T11	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488287515	3162069	0	0
DepthKnown_A	488287515	488150183	0	0
RvalidKnown_A	488287515	488150183	0	0
WreadyKnown_A	488287515	488150183	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	3162069	0	0
T1	242750	832	0	0
T2	154066	8471	0	0
T3	70650	837	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	9984	0	0
T8	96272	3927	0	0
T9	275077	9476	0	0
T10	123063	832	0	0
T11	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488287515	193214	0	0
DepthKnown_A	488287515	488150183	0	0
RvalidKnown_A	488287515	488150183	0	0
WreadyKnown_A	488287515	488150183	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	193214	0	0
T2	154066	64	0	0
T3	70650	0	0	0
T4	3260	0	0	0
T5	1326	0	0	0
T6	4752	0	0	0
T7	291198	352	0	0
T8	96272	0	0	0
T9	275077	1172	0	0
T10	123063	0	0	0
T11	11861	0	0	0
T24	0	395	0	0
T25	0	128	0	0
T27	0	640	0	0
T30	0	161	0	0
T31	0	36	0	0
T32	0	29	0	0
T40	0	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488287515	432010	0	0
DepthKnown_A	488287515	488150183	0	0
RvalidKnown_A	488287515	488150183	0	0
WreadyKnown_A	488287515	488150183	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	432010	0	0
T2	154066	285	0	0
T3	70650	0	0	0
T4	3260	0	0	0
T5	1326	0	0	0
T6	4752	0	0	0
T7	291198	352	0	0
T8	96272	0	0	0
T9	275077	3228	0	0
T10	123063	0	0	0
T11	11861	0	0	0
T24	0	1836	0	0
T25	0	615	0	0
T27	0	640	0	0
T30	0	467	0	0
T31	0	147	0	0
T32	0	29	0	0
T40	0	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488287515	6588343	0	0
DepthKnown_A	488287515	488150183	0	0
RvalidKnown_A	488287515	488150183	0	0
WreadyKnown_A	488287515	488150183	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	6588343	0	0
T1	242750	362	0	0
T2	154066	435	0	0
T3	70650	53	0	0
T4	3260	60	0	0
T5	1326	61	0	0
T6	4752	50	0	0
T7	291198	4844	0	0
T8	96272	2630	0	0
T9	275077	9178	0	0
T10	123063	5190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488287515	13158992	0	0
DepthKnown_A	488287515	488150183	0	0
RvalidKnown_A	488287515	488150183	0	0
WreadyKnown_A	488287515	488150183	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	13158992	0	0
T1	242750	1515	0	0
T2	154066	1825	0	0
T3	70650	235	0	0
T4	3260	119	0	0
T5	1326	61	0	0
T6	4752	104	0	0
T7	291198	4841	0	0
T8	96272	11304	0	0
T9	275077	23749	0	0
T10	123063	5190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488287515	488150183	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0