Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T24,T27
1	0	Covered	T9,T24,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T24,T26
1	0	Unreachable
1	1	Covered	T9,T24,T27

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	782308027	632756315	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	782308027	3783555	0	0
GntImpliesValid_A	782308027	3783555	0	0
GrantKnown_A	782308027	632756315	0	0
IdxKnown_A	782308027	632756315	0	0
IndexIsCorrect_A	782308027	3783555	0	0
LockArbDecision_A	782308027	0	0	0
NoReadyValidNoGrant_A	782308027	0	0	0
ReadyAndValidImplyGrant_A	782308027	3783555	0	0
ReqAndReadyImplyGrant_A	782308027	3783555	0	0
ReqImpliesValid_A	782308027	3783555	0	0
ReqStaysHighUntilGranted0_M	782308027	0	0	0
RoundRobin_A	782308027	7	0	976
ValidKnown_A	782308027	632756315	0	0
gen_data_port_assertion.DataFlow_A	782308027	3783555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	632756315	0	0
T1	302626	302118	0	0
T2	279856	279471	0	0
T3	133668	133145	0	0
T4	3604	3530	0	0
T5	1326	1271	0	0
T6	11062	10998	0	0
T7	762171	757168	0	0
T8	124656	124574	0	0
T9	1778829	1020508	0	0
T10	163257	142944	0	0
T11	17344	8672	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	3783555	0	0
T1	242750	832	0	0
T2	279856	2822	0	0
T3	133668	832	0	0
T4	3604	832	0	0
T5	1326	0	0	0
T6	11062	832	0	0
T7	762171	13535	0	0
T8	124656	832	0	0
T9	1778829	18755	0	0
T10	163257	832	0	0
T11	17344	832	0	0
T12	404496	0	0	0
T13	0	8979	0	0
T24	211048	3984	0	0
T25	42028	1028	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T30	0	3563	0	0
T31	0	259	0	0
T32	0	220	0	0
T33	0	7560	0	0
T34	0	4255	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	3783555	0	0
T1	242750	832	0	0
T2	279856	2822	0	0
T3	133668	832	0	0
T4	3604	832	0	0
T5	1326	0	0	0
T6	11062	832	0	0
T7	762171	13535	0	0
T8	124656	832	0	0
T9	1778829	18755	0	0
T10	163257	832	0	0
T11	17344	832	0	0
T12	404496	0	0	0
T13	0	8979	0	0
T24	211048	3984	0	0
T25	42028	1028	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T30	0	3563	0	0
T31	0	259	0	0
T32	0	220	0	0
T33	0	7560	0	0
T34	0	4255	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	632756315	0	0
T1	302626	302118	0	0
T2	279856	279471	0	0
T3	133668	133145	0	0
T4	3604	3530	0	0
T5	1326	1271	0	0
T6	11062	10998	0	0
T7	762171	757168	0	0
T8	124656	124574	0	0
T9	1778829	1020508	0	0
T10	163257	142944	0	0
T11	17344	8672	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	632756315	0	0
T1	302626	302118	0	0
T2	279856	279471	0	0
T3	133668	133145	0	0
T4	3604	3530	0	0
T5	1326	1271	0	0
T6	11062	10998	0	0
T7	762171	757168	0	0
T8	124656	124574	0	0
T9	1778829	1020508	0	0
T10	163257	142944	0	0
T11	17344	8672	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	3783555	0	0
T1	242750	832	0	0
T2	279856	2822	0	0
T3	133668	832	0	0
T4	3604	832	0	0
T5	1326	0	0	0
T6	11062	832	0	0
T7	762171	13535	0	0
T8	124656	832	0	0
T9	1778829	18755	0	0
T10	163257	832	0	0
T11	17344	832	0	0
T12	404496	0	0	0
T13	0	8979	0	0
T24	211048	3984	0	0
T25	42028	1028	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T30	0	3563	0	0
T31	0	259	0	0
T32	0	220	0	0
T33	0	7560	0	0
T34	0	4255	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	3783555	0	0
T1	242750	832	0	0
T2	279856	2822	0	0
T3	133668	832	0	0
T4	3604	832	0	0
T5	1326	0	0	0
T6	11062	832	0	0
T7	762171	13535	0	0
T8	124656	832	0	0
T9	1778829	18755	0	0
T10	163257	832	0	0
T11	17344	832	0	0
T12	404496	0	0	0
T13	0	8979	0	0
T24	211048	3984	0	0
T25	42028	1028	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T30	0	3563	0	0
T31	0	259	0	0
T32	0	220	0	0
T33	0	7560	0	0
T34	0	4255	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	3783555	0	0
T1	242750	832	0	0
T2	279856	2822	0	0
T3	133668	832	0	0
T4	3604	832	0	0
T5	1326	0	0	0
T6	11062	832	0	0
T7	762171	13535	0	0
T8	124656	832	0	0
T9	1778829	18755	0	0
T10	163257	832	0	0
T11	17344	832	0	0
T12	404496	0	0	0
T13	0	8979	0	0
T24	211048	3984	0	0
T25	42028	1028	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T30	0	3563	0	0
T31	0	259	0	0
T32	0	220	0	0
T33	0	7560	0	0
T34	0	4255	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	3783555	0	0
T1	242750	832	0	0
T2	279856	2822	0	0
T3	133668	832	0	0
T4	3604	832	0	0
T5	1326	0	0	0
T6	11062	832	0	0
T7	762171	13535	0	0
T8	124656	832	0	0
T9	1778829	18755	0	0
T10	163257	832	0	0
T11	17344	832	0	0
T12	404496	0	0	0
T13	0	8979	0	0
T24	211048	3984	0	0
T25	42028	1028	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T30	0	3563	0	0
T31	0	259	0	0
T32	0	220	0	0
T33	0	7560	0	0
T34	0	4255	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	7	0	976
T13	492694	0	0	1
T14	285019	0	0	1
T35	301259	1	0	1
T37	1461	0	0	1
T41	252519	0	0	1
T49	593534	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	10330	0	0	1
T57	121546	0	0	1
T58	44718	0	0	1
T59	3592	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	632756315	0	0
T1	302626	302118	0	0
T2	279856	279471	0	0
T3	133668	133145	0	0
T4	3604	3530	0	0
T5	1326	1271	0	0
T6	11062	10998	0	0
T7	762171	757168	0	0
T8	124656	124574	0	0
T9	1778829	1020508	0	0
T10	163257	142944	0	0
T11	17344	8672	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782308027	3783555	0	0
T1	242750	832	0	0
T2	279856	2822	0	0
T3	133668	832	0	0
T4	3604	832	0	0
T5	1326	0	0	0
T6	11062	832	0	0
T7	762171	13535	0	0
T8	124656	832	0	0
T9	1778829	18755	0	0
T10	163257	832	0	0
T11	17344	832	0	0
T12	404496	0	0	0
T13	0	8979	0	0
T24	211048	3984	0	0
T25	42028	1028	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T30	0	3563	0	0
T31	0	259	0	0
T32	0	220	0	0
T33	0	7560	0	0
T34	0	4255	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T24,T27
1	0	Covered	T9,T24,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T24,T26
1	0	Unreachable
1	1	Covered	T9,T24,T27

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T24,T27
0	0	1	Unreachable
0	0	0	Covered	T9,T24,T26

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T24,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T24,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	148123149	27558693	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	148123149	630532	0	0
GntImpliesValid_A	148123149	630532	0	0
GrantKnown_A	148123149	27558693	0	0
IdxKnown_A	148123149	27558693	0	0
IndexIsCorrect_A	148123149	630532	0	0
LockArbDecision_A	148123149	0	0	0
NoReadyValidNoGrant_A	148123149	0	0	0
ReadyAndValidImplyGrant_A	148123149	630532	0	0
ReqAndReadyImplyGrant_A	148123149	630532	0	0
ReqImpliesValid_A	148123149	630532	0	0
ReqStaysHighUntilGranted0_M	148123149	0	0	0
RoundRobin_A	148123149	0	0	0
ValidKnown_A	148123149	27558693	0	0
gen_data_port_assertion.DataFlow_A	148123149	630532	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	27558693	0	0
T9	751876	420360	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	630532	0	0
T9	751876	4871	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T13	0	8979	0	0
T24	211048	1408	0	0
T25	42028	0	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T31	0	253	0	0
T32	0	220	0	0
T33	0	1395	0	0
T34	0	1302	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	630532	0	0
T9	751876	4871	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T13	0	8979	0	0
T24	211048	1408	0	0
T25	42028	0	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T31	0	253	0	0
T32	0	220	0	0
T33	0	1395	0	0
T34	0	1302	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	27558693	0	0
T9	751876	420360	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	27558693	0	0
T9	751876	420360	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	630532	0	0
T9	751876	4871	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T13	0	8979	0	0
T24	211048	1408	0	0
T25	42028	0	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T31	0	253	0	0
T32	0	220	0	0
T33	0	1395	0	0
T34	0	1302	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	630532	0	0
T9	751876	4871	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T13	0	8979	0	0
T24	211048	1408	0	0
T25	42028	0	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T31	0	253	0	0
T32	0	220	0	0
T33	0	1395	0	0
T34	0	1302	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	630532	0	0
T9	751876	4871	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T13	0	8979	0	0
T24	211048	1408	0	0
T25	42028	0	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T31	0	253	0	0
T32	0	220	0	0
T33	0	1395	0	0
T34	0	1302	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	630532	0	0
T9	751876	4871	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T13	0	8979	0	0
T24	211048	1408	0	0
T25	42028	0	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T31	0	253	0	0
T32	0	220	0	0
T33	0	1395	0	0
T34	0	1302	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	27558693	0	0
T9	751876	420360	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	211048	31432	0	0
T25	42028	0	0	0
T26	144	144	0	0
T27	312417	306840	0	0
T29	792	792	0	0
T30	0	6	0	0
T31	0	6320	0	0
T32	0	25968	0	0
T33	0	36136	0	0
T34	0	32352	0	0
T44	9806	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	630532	0	0
T9	751876	4871	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T13	0	8979	0	0
T24	211048	1408	0	0
T25	42028	0	0	0
T26	144	0	0	0
T27	312417	3776	0	0
T29	792	0	0	0
T31	0	253	0	0
T32	0	220	0	0
T33	0	1395	0	0
T34	0	1302	0	0
T35	0	5621	0	0
T44	9806	0	0	0
T49	0	4890	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	148123149	119227194	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	148123149	818917	0	0
GntImpliesValid_A	148123149	818917	0	0
GrantKnown_A	148123149	119227194	0	0
IdxKnown_A	148123149	119227194	0	0
IndexIsCorrect_A	148123149	818917	0	0
LockArbDecision_A	148123149	0	0	0
NoReadyValidNoGrant_A	148123149	0	0	0
ReadyAndValidImplyGrant_A	148123149	818917	0	0
ReqAndReadyImplyGrant_A	148123149	818917	0	0
ReqImpliesValid_A	148123149	818917	0	0
ReqStaysHighUntilGranted0_M	148123149	0	0	0
RoundRobin_A	148123149	0	0	0
ValidKnown_A	148123149	119227194	0	0
gen_data_port_assertion.DataFlow_A	148123149	818917	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	119227194	0	0
T1	59876	59462	0	0
T2	125790	125485	0	0
T3	63018	62566	0	0
T4	344	344	0	0
T6	6310	6310	0	0
T7	470973	465980	0	0
T8	28384	28384	0	0
T9	751876	325327	0	0
T10	20097	19952	0	0
T11	8672	8672	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	818917	0	0
T2	125790	259	0	0
T3	63018	0	0	0
T4	344	0	0	0
T6	6310	0	0	0
T7	470973	3176	0	0
T8	28384	0	0	0
T9	751876	5293	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	0	2576	0	0
T25	0	1028	0	0
T30	0	3563	0	0
T31	0	6	0	0
T33	0	6165	0	0
T34	0	2953	0	0
T40	0	4802	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	818917	0	0
T2	125790	259	0	0
T3	63018	0	0	0
T4	344	0	0	0
T6	6310	0	0	0
T7	470973	3176	0	0
T8	28384	0	0	0
T9	751876	5293	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	0	2576	0	0
T25	0	1028	0	0
T30	0	3563	0	0
T31	0	6	0	0
T33	0	6165	0	0
T34	0	2953	0	0
T40	0	4802	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	119227194	0	0
T1	59876	59462	0	0
T2	125790	125485	0	0
T3	63018	62566	0	0
T4	344	344	0	0
T6	6310	6310	0	0
T7	470973	465980	0	0
T8	28384	28384	0	0
T9	751876	325327	0	0
T10	20097	19952	0	0
T11	8672	8672	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	119227194	0	0
T1	59876	59462	0	0
T2	125790	125485	0	0
T3	63018	62566	0	0
T4	344	344	0	0
T6	6310	6310	0	0
T7	470973	465980	0	0
T8	28384	28384	0	0
T9	751876	325327	0	0
T10	20097	19952	0	0
T11	8672	8672	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	818917	0	0
T2	125790	259	0	0
T3	63018	0	0	0
T4	344	0	0	0
T6	6310	0	0	0
T7	470973	3176	0	0
T8	28384	0	0	0
T9	751876	5293	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	0	2576	0	0
T25	0	1028	0	0
T30	0	3563	0	0
T31	0	6	0	0
T33	0	6165	0	0
T34	0	2953	0	0
T40	0	4802	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	818917	0	0
T2	125790	259	0	0
T3	63018	0	0	0
T4	344	0	0	0
T6	6310	0	0	0
T7	470973	3176	0	0
T8	28384	0	0	0
T9	751876	5293	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	0	2576	0	0
T25	0	1028	0	0
T30	0	3563	0	0
T31	0	6	0	0
T33	0	6165	0	0
T34	0	2953	0	0
T40	0	4802	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	818917	0	0
T2	125790	259	0	0
T3	63018	0	0	0
T4	344	0	0	0
T6	6310	0	0	0
T7	470973	3176	0	0
T8	28384	0	0	0
T9	751876	5293	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	0	2576	0	0
T25	0	1028	0	0
T30	0	3563	0	0
T31	0	6	0	0
T33	0	6165	0	0
T34	0	2953	0	0
T40	0	4802	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	818917	0	0
T2	125790	259	0	0
T3	63018	0	0	0
T4	344	0	0	0
T6	6310	0	0	0
T7	470973	3176	0	0
T8	28384	0	0	0
T9	751876	5293	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	0	2576	0	0
T25	0	1028	0	0
T30	0	3563	0	0
T31	0	6	0	0
T33	0	6165	0	0
T34	0	2953	0	0
T40	0	4802	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	119227194	0	0
T1	59876	59462	0	0
T2	125790	125485	0	0
T3	63018	62566	0	0
T4	344	344	0	0
T6	6310	6310	0	0
T7	470973	465980	0	0
T8	28384	28384	0	0
T9	751876	325327	0	0
T10	20097	19952	0	0
T11	8672	8672	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148123149	818917	0	0
T2	125790	259	0	0
T3	63018	0	0	0
T4	344	0	0	0
T6	6310	0	0	0
T7	470973	3176	0	0
T8	28384	0	0	0
T9	751876	5293	0	0
T10	20097	0	0	0
T11	8672	0	0	0
T12	202248	0	0	0
T24	0	2576	0	0
T25	0	1028	0	0
T30	0	3563	0	0
T31	0	6	0	0
T33	0	6165	0	0
T34	0	2953	0	0
T40	0	4802	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	486061729	485970428	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	486061729	2334106	0	0
GntImpliesValid_A	486061729	2334106	0	0
GrantKnown_A	486061729	485970428	0	0
IdxKnown_A	486061729	485970428	0	0
IndexIsCorrect_A	486061729	2334106	0	0
LockArbDecision_A	486061729	0	0	0
NoReadyValidNoGrant_A	486061729	0	0	0
ReadyAndValidImplyGrant_A	486061729	2334106	0	0
ReqAndReadyImplyGrant_A	486061729	2334106	0	0
ReqImpliesValid_A	486061729	2334106	0	0
ReqStaysHighUntilGranted0_M	486061729	0	0	0
RoundRobin_A	486061729	7	0	976
ValidKnown_A	486061729	485970428	0	0
gen_data_port_assertion.DataFlow_A	486061729	2334106	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	485970428	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	2334106	0	0
T1	242750	832	0	0
T2	154066	2563	0	0
T3	70650	832	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	10359	0	0
T8	96272	832	0	0
T9	275077	8591	0	0
T10	123063	832	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	2334106	0	0
T1	242750	832	0	0
T2	154066	2563	0	0
T3	70650	832	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	10359	0	0
T8	96272	832	0	0
T9	275077	8591	0	0
T10	123063	832	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	485970428	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	485970428	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	2334106	0	0
T1	242750	832	0	0
T2	154066	2563	0	0
T3	70650	832	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	10359	0	0
T8	96272	832	0	0
T9	275077	8591	0	0
T10	123063	832	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	2334106	0	0
T1	242750	832	0	0
T2	154066	2563	0	0
T3	70650	832	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	10359	0	0
T8	96272	832	0	0
T9	275077	8591	0	0
T10	123063	832	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	2334106	0	0
T1	242750	832	0	0
T2	154066	2563	0	0
T3	70650	832	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	10359	0	0
T8	96272	832	0	0
T9	275077	8591	0	0
T10	123063	832	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	2334106	0	0
T1	242750	832	0	0
T2	154066	2563	0	0
T3	70650	832	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	10359	0	0
T8	96272	832	0	0
T9	275077	8591	0	0
T10	123063	832	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	7	0	976
T13	492694	0	0	1
T14	285019	0	0	1
T35	301259	1	0	1
T37	1461	0	0	1
T41	252519	0	0	1
T49	593534	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	10330	0	0	1
T57	121546	0	0	1
T58	44718	0	0	1
T59	3592	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	485970428	0	0
T1	242750	242656	0	0
T2	154066	153986	0	0
T3	70650	70579	0	0
T4	3260	3186	0	0
T5	1326	1271	0	0
T6	4752	4688	0	0
T7	291198	291188	0	0
T8	96272	96190	0	0
T9	275077	274821	0	0
T10	123063	122992	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486061729	2334106	0	0
T1	242750	832	0	0
T2	154066	2563	0	0
T3	70650	832	0	0
T4	3260	832	0	0
T5	1326	0	0	0
T6	4752	832	0	0
T7	291198	10359	0	0
T8	96272	832	0	0
T9	275077	8591	0	0
T10	123063	832	0	0
T11	0	832	0	0