Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3989809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4548625

1

T1

896

T2

877

T3

1236

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4701655	1			T1	9		T2	4		T3	719
values[0x0]	1916475	1			T1	440		T2	442		T3	445
values[0x1]	1920304	1			T1	452		T2	437		T3	448

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2819732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5718702

1

T1

897

T2

879

T3

1311

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30951	1			T1	3		T2	5		T3	4
valid_sources[0x01]	34228	1			T1	6		T2	4		T3	10
valid_sources[0x02]	32172	1			T1	1		T2	5		T3	5
valid_sources[0x03]	31262	1			T1	3		T3	10		T4	5
valid_sources[0x04]	38196	1			T1	1		T2	3		T3	9
valid_sources[0x05]	33928	1			T1	6		T2	2		T3	6
valid_sources[0x06]	34316	1			T1	3		T2	2		T3	6
valid_sources[0x07]	33582	1			T1	3		T2	5		T3	2
valid_sources[0x08]	32239	1			T1	4		T2	2		T3	2
valid_sources[0x09]	30023	1			T1	2		T2	4		T3	11
valid_sources[0x0a]	30252	1			T1	6		T3	7		T4	10
valid_sources[0x0b]	40960	1			T1	6		T2	2		T3	8
valid_sources[0x0c]	34406	1			T1	3		T3	6		T4	13
valid_sources[0x0d]	37268	1			T1	4		T2	7		T3	7
valid_sources[0x0e]	33126	1			T1	4		T2	4		T3	5
valid_sources[0x0f]	32614	1			T1	1		T2	5		T3	8
valid_sources[0x10]	29750	1			T1	3		T2	4		T3	6
valid_sources[0x11]	34422	1			T1	2		T2	6		T3	13
valid_sources[0x12]	32062	1			T1	2		T2	5		T3	11
valid_sources[0x13]	32617	1			T1	1		T3	5		T4	10
valid_sources[0x14]	31869	1			T1	1		T2	2		T3	8
valid_sources[0x15]	32130	1			T1	1		T2	5		T3	6
valid_sources[0x16]	31940	1			T1	13		T2	4		T3	9
valid_sources[0x17]	34273	1			T1	5		T2	5		T3	5
valid_sources[0x18]	31458	1			T1	1		T2	1		T3	3
valid_sources[0x19]	31506	1			T1	3		T2	1		T3	7
valid_sources[0x1a]	30706	1			T1	3		T2	3		T3	8
valid_sources[0x1b]	33874	1			T1	7		T2	5		T3	1
valid_sources[0x1c]	33018	1			T1	5		T2	4		T3	6
valid_sources[0x1d]	31922	1			T1	2		T2	2		T3	6
valid_sources[0x1e]	33278	1			T1	7		T2	3		T3	9
valid_sources[0x1f]	30136	1			T1	3		T2	5		T4	10
valid_sources[0x20]	31383	1			T1	3		T2	2		T3	2
valid_sources[0x21]	35037	1			T1	1		T2	3		T3	10
valid_sources[0x22]	33006	1			T1	2		T2	2		T3	12
valid_sources[0x23]	34712	1			T1	5		T2	1		T3	7
valid_sources[0x24]	30297	1			T1	6		T2	6		T3	7
valid_sources[0x25]	34336	1			T1	1		T2	6		T3	8
valid_sources[0x26]	33602	1			T1	3		T3	4		T4	8
valid_sources[0x27]	31113	1			T1	1		T2	8		T3	2
valid_sources[0x28]	33014	1			T1	7		T2	3		T3	6
valid_sources[0x29]	36774	1			T1	9		T2	4		T3	6
valid_sources[0x2a]	32171	1			T1	1		T2	2		T3	6
valid_sources[0x2b]	32790	1			T1	3		T2	3		T3	2
valid_sources[0x2c]	29442	1			T1	2		T2	2		T3	11
valid_sources[0x2d]	30178	1			T1	1		T2	2		T3	10
valid_sources[0x2e]	31770	1			T1	3		T2	4		T3	4
valid_sources[0x2f]	29184	1			T1	1		T2	3		T3	8
valid_sources[0x30]	33064	1			T1	5		T2	3		T3	4
valid_sources[0x31]	37721	1			T1	4		T2	2		T3	5
valid_sources[0x32]	34131	1			T1	1		T2	1		T3	5
valid_sources[0x33]	33985	1			T2	4		T3	7		T4	6
valid_sources[0x34]	34480	1			T1	2		T2	7		T3	7
valid_sources[0x35]	30363	1			T1	9		T2	4		T3	7
valid_sources[0x36]	33782	1			T1	5		T2	6		T3	5
valid_sources[0x37]	32431	1			T1	1		T2	4		T3	14
valid_sources[0x38]	36915	1			T1	7		T2	5		T3	5
valid_sources[0x39]	35259	1			T1	2		T2	1		T3	2
valid_sources[0x3a]	35736	1			T1	5		T2	6		T4	3
valid_sources[0x3b]	39294	1			T1	2		T2	2		T3	8
valid_sources[0x3c]	34451	1			T1	2		T2	4		T3	10
valid_sources[0x3d]	35862	1			T1	5		T2	4		T3	3
valid_sources[0x3e]	30914	1			T1	3		T2	3		T3	9
valid_sources[0x3f]	31036	1			T1	7		T2	2		T3	7
valid_sources[0x40]	33340	1			T1	7		T2	4		T3	11
valid_sources[0x41]	33266	1			T1	2		T2	1		T3	4
valid_sources[0x42]	36515	1			T1	4		T2	2		T3	5
valid_sources[0x43]	35202	1			T1	4		T2	1		T3	5
valid_sources[0x44]	28635	1			T1	2		T2	3		T3	3
valid_sources[0x45]	33073	1			T2	6		T3	2		T4	7
valid_sources[0x46]	33824	1			T2	1		T3	8		T4	8
valid_sources[0x47]	31758	1			T1	7		T3	6		T4	6
valid_sources[0x48]	35150	1			T1	3		T2	2		T3	6
valid_sources[0x49]	32019	1			T1	3		T2	2		T3	9
valid_sources[0x4a]	35705	1			T1	4		T2	5		T3	7
valid_sources[0x4b]	34354	1			T2	1		T3	12		T4	4
valid_sources[0x4c]	31597	1			T1	2		T2	6		T3	3
valid_sources[0x4d]	34883	1			T1	5		T2	4		T3	5
valid_sources[0x4e]	30626	1			T2	3		T3	8		T4	9
valid_sources[0x4f]	30889	1			T1	3		T2	1		T3	13
valid_sources[0x50]	34544	1			T1	2		T2	7		T3	9
valid_sources[0x51]	30392	1			T1	6		T2	5		T3	5
valid_sources[0x52]	33044	1			T1	7		T2	1		T3	8
valid_sources[0x53]	40707	1			T1	1		T2	2		T3	7
valid_sources[0x54]	33992	1			T1	4		T2	3		T3	4
valid_sources[0x55]	32485	1			T1	2		T2	1		T3	6
valid_sources[0x56]	29869	1			T1	2		T2	5		T3	1
valid_sources[0x57]	39134	1			T1	4		T2	2		T3	4
valid_sources[0x58]	32290	1			T1	4		T2	4		T3	6
valid_sources[0x59]	31220	1			T1	3		T2	1		T3	3
valid_sources[0x5a]	35496	1			T1	3		T2	4		T3	3
valid_sources[0x5b]	36193	1			T1	3		T2	4		T3	5
valid_sources[0x5c]	32959	1			T1	4		T2	4		T3	5
valid_sources[0x5d]	33892	1			T1	5		T2	1		T3	2
valid_sources[0x5e]	31586	1			T1	3		T2	9		T3	6
valid_sources[0x5f]	32113	1			T1	7		T2	2		T3	6
valid_sources[0x60]	30901	1			T1	2		T2	8		T3	8
valid_sources[0x61]	32772	1			T1	3		T2	3		T3	4
valid_sources[0x62]	31794	1			T1	3		T2	3		T3	6
valid_sources[0x63]	32213	1			T1	2		T2	2		T3	7
valid_sources[0x64]	32660	1			T1	2		T2	6		T3	7
valid_sources[0x65]	33404	1			T1	1		T3	5		T4	3
valid_sources[0x66]	31146	1			T1	4		T2	2		T3	5
valid_sources[0x67]	30581	1			T1	8		T2	3		T3	4
valid_sources[0x68]	35458	1			T1	1		T2	6		T3	5
valid_sources[0x69]	36147	1			T1	4		T2	4		T3	9
valid_sources[0x6a]	33583	1			T1	3		T2	3		T3	7
valid_sources[0x6b]	35285	1			T1	9		T2	3		T3	8
valid_sources[0x6c]	32209	1			T1	3		T2	3		T3	5
valid_sources[0x6d]	30656	1			T1	1		T2	2		T3	7
valid_sources[0x6e]	34714	1			T1	3		T2	2		T3	3
valid_sources[0x6f]	29799	1			T1	5		T2	2		T3	9
valid_sources[0x70]	30877	1			T1	4		T2	4		T3	9
valid_sources[0x71]	34175	1			T1	6		T2	3		T3	8
valid_sources[0x72]	30831	1			T1	3		T2	7		T3	10
valid_sources[0x73]	32476	1			T1	2		T2	4		T3	6
valid_sources[0x74]	34758	1			T1	1		T2	3		T3	7
valid_sources[0x75]	30427	1			T1	3		T2	6		T3	14
valid_sources[0x76]	33387	1			T1	1		T2	2		T3	6
valid_sources[0x77]	36498	1			T1	3		T2	2		T3	4
valid_sources[0x78]	32739	1			T1	1		T2	3		T3	5
valid_sources[0x79]	31587	1			T1	1		T2	6		T3	6
valid_sources[0x7a]	29819	1			T1	6		T2	7		T3	4
valid_sources[0x7b]	32406	1			T1	2		T2	2		T3	5
valid_sources[0x7c]	38798	1			T2	6		T3	9		T4	8
valid_sources[0x7d]	32648	1			T1	1		T2	3		T3	5
valid_sources[0x7e]	35661	1			T1	2		T2	2		T3	3
valid_sources[0x7f]	36556	1			T1	9		T2	1		T3	10
valid_sources[0x80]	49038	1			T1	4		T2	2		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1088042

1

T1

6

T2

1

T3

345

values[0x0]

all_enables

biggest_size

1741897

1

T1

438

T2

441

T3

444

values[0x1]

all_enables

biggest_size

1718686

1

T1

452

T2

435

T3

447