Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4010298

1

T1

5

T2

6

T3

376

full_word

4547751

1

T1

896

T2

877

T3

1236

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8557699	1			T1	901		T2	883		T3	1612
auto[TlIntgErrCmd]	123	1			T101	6		T102	7		T103	13
auto[TlIntgErrData]	111	1			T101	2		T102	12		T103	9
auto[TlIntgErrBoth]	116	1			T101	2		T102	11		T103	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4703237

1

T1

9

T2

4

T3

719

auto[1]

3854812

1

T1

892

T2

879

T3

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3614976	1			T1	3		T2	3		T3	374
auto[TlIntgErrNone]	partial	auto[1]	394997	1			T1	2		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1088118	1			T1	6		T2	1		T3	345
auto[TlIntgErrNone]	full_word	auto[1]	3459608	1			T1	890		T2	876		T3	891
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T101	3		T103	3		T154	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T101	2		T102	6		T103	8
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T180	1		T179	1		T177	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T101	1		T102	1		T103	2
auto[TlIntgErrData]	partial	auto[0]	44	1			T101	2		T102	4		T103	5
auto[TlIntgErrData]	partial	auto[1]	59	1			T102	7		T103	4		T154	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T102	1		T181	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T181	2		T183	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T101	2		T102	3		T103	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T102	7		T103	5		T154	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T103	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T102	1		T103	1		T177	1