Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	502805815	3017849	0	0
DepthKnown_A	502805815	502676275	0	0
RvalidKnown_A	502805815	502676275	0	0
WreadyKnown_A	502805815	502676275	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	3017849	0	0
T1	192396	1663	0	0
T2	287123	1663	0	0
T3	486907	1667	0	0
T4	23035	1663	0	0
T5	219237	1663	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	0	0	0
T10	335895	13316	0	0
T11	0	1663	0	0
T12	0	16635	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	502805815	3398525	0	0
DepthKnown_A	502805815	502676275	0	0
RvalidKnown_A	502805815	502676275	0	0
WreadyKnown_A	502805815	502676275	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	3398525	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	836	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	3755	0	0
T7	789	0	0	0
T8	176618	3723	0	0
T9	7174	0	0	0
T10	335895	33728	0	0
T11	0	832	0	0
T12	0	25023	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	502805815	208719	0	0
DepthKnown_A	502805815	502676275	0	0
RvalidKnown_A	502805815	502676275	0	0
WreadyKnown_A	502805815	502676275	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	208719	0	0
T9	7174	43	0	0
T10	335895	750	0	0
T11	234843	0	0	0
T12	613553	992	0	0
T13	424982	590	0	0
T23	146715	80	0	0
T24	1417	0	0	0
T25	6665	18	0	0
T26	331185	403	0	0
T27	13290	0	0	0
T31	0	1098	0	0
T40	0	322	0	0
T41	0	535	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	502805815	470715	0	0
DepthKnown_A	502805815	502676275	0	0
RvalidKnown_A	502805815	502676275	0	0
WreadyKnown_A	502805815	502676275	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	470715	0	0
T9	7174	43	0	0
T10	335895	3504	0	0
T11	234843	0	0	0
T12	613553	3117	0	0
T13	424982	590	0	0
T23	146715	80	0	0
T24	1417	0	0	0
T25	6665	18	0	0
T26	331185	1276	0	0
T27	13290	0	0	0
T31	0	3609	0	0
T40	0	873	0	0
T41	0	535	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	502805815	6736848	0	0
DepthKnown_A	502805815	502676275	0	0
RvalidKnown_A	502805815	502676275	0	0
WreadyKnown_A	502805815	502676275	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	6736848	0	0
T1	192396	69	0	0
T2	287123	51	0	0
T3	486907	786	0	0
T4	23035	1021	0	0
T5	219237	7934	0	0
T6	21857	56	0	0
T7	789	6	0	0
T8	176618	73	0	0
T9	7174	414	0	0
T10	335895	33638	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	502805815	14442357	0	0
DepthKnown_A	502805815	502676275	0	0
RvalidKnown_A	502805815	502676275	0	0
WreadyKnown_A	502805815	502676275	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	14442357	0	0
T1	192396	69	0	0
T2	287123	51	0	0
T3	486907	3372	0	0
T4	23035	1020	0	0
T5	219237	24388	0	0
T6	21857	240	0	0
T7	789	6	0	0
T8	176618	346	0	0
T9	7174	414	0	0
T10	335895	133601	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502805815	502676275	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0