Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T12
1	0	Covered	T9,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Unreachable
1	1	Covered	T9,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T23

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T23
1	0	Covered	T10,T12,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T10,T12,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	815787834	656704324	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	815787834	4021702	0	0
GntImpliesValid_A	815787834	4021702	0	0
GrantKnown_A	815787834	656704324	0	0
IdxKnown_A	815787834	656704324	0	0
IndexIsCorrect_A	815787834	4021702	0	0
LockArbDecision_A	815787834	0	0	0
NoReadyValidNoGrant_A	815787834	0	0	0
ReadyAndValidImplyGrant_A	815787834	4021702	0	0
ReqAndReadyImplyGrant_A	815787834	4021702	0	0
ReqImpliesValid_A	815787834	4021702	0	0
ReqStaysHighUntilGranted0_M	815787834	0	0	0
RoundRobin_A	815787834	3	0	974
ValidKnown_A	815787834	656704324	0	0
gen_data_port_assertion.DataFlow_A	815787834	4021702	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	656704324	0	0
T1	255290	255233	0	0
T2	334499	334439	0	0
T3	647750	647243	0	0
T4	39187	38713	0	0
T5	327111	326690	0	0
T6	42709	42188	0	0
T7	789	690	0	0
T8	230867	230365	0	0
T9	16212	11398	0	0
T10	1285923	804509	0	0
T11	153870	76668	0	0
T12	102675	1016683	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	4021702	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	11693	332	0	0
T10	1285923	18281	0	0
T11	153870	832	0	0
T12	205350	5704	0	0
T13	211238	3965	0	0
T14	0	4574	0	0
T23	407916	339	0	0
T24	432	0	0	0
T25	5456	127	0	0
T26	1615738	8145	0	0
T27	2388	0	0	0
T29	12376	0	0	0
T31	0	10981	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T40	0	1559	0	0
T49	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	4021702	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	11693	332	0	0
T10	1285923	18281	0	0
T11	153870	832	0	0
T12	205350	5704	0	0
T13	211238	3965	0	0
T14	0	4574	0	0
T23	407916	339	0	0
T24	432	0	0	0
T25	5456	127	0	0
T26	1615738	8145	0	0
T27	2388	0	0	0
T29	12376	0	0	0
T31	0	10981	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T40	0	1559	0	0
T49	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	656704324	0	0
T1	255290	255233	0	0
T2	334499	334439	0	0
T3	647750	647243	0	0
T4	39187	38713	0	0
T5	327111	326690	0	0
T6	42709	42188	0	0
T7	789	690	0	0
T8	230867	230365	0	0
T9	16212	11398	0	0
T10	1285923	804509	0	0
T11	153870	76668	0	0
T12	102675	1016683	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	656704324	0	0
T1	255290	255233	0	0
T2	334499	334439	0	0
T3	647750	647243	0	0
T4	39187	38713	0	0
T5	327111	326690	0	0
T6	42709	42188	0	0
T7	789	690	0	0
T8	230867	230365	0	0
T9	16212	11398	0	0
T10	1285923	804509	0	0
T11	153870	76668	0	0
T12	102675	1016683	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	4021702	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	11693	332	0	0
T10	1285923	18281	0	0
T11	153870	832	0	0
T12	205350	5704	0	0
T13	211238	3965	0	0
T14	0	4574	0	0
T23	407916	339	0	0
T24	432	0	0	0
T25	5456	127	0	0
T26	1615738	8145	0	0
T27	2388	0	0	0
T29	12376	0	0	0
T31	0	10981	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T40	0	1559	0	0
T49	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	4021702	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	11693	332	0	0
T10	1285923	18281	0	0
T11	153870	832	0	0
T12	205350	5704	0	0
T13	211238	3965	0	0
T14	0	4574	0	0
T23	407916	339	0	0
T24	432	0	0	0
T25	5456	127	0	0
T26	1615738	8145	0	0
T27	2388	0	0	0
T29	12376	0	0	0
T31	0	10981	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T40	0	1559	0	0
T49	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	4021702	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	11693	332	0	0
T10	1285923	18281	0	0
T11	153870	832	0	0
T12	205350	5704	0	0
T13	211238	3965	0	0
T14	0	4574	0	0
T23	407916	339	0	0
T24	432	0	0	0
T25	5456	127	0	0
T26	1615738	8145	0	0
T27	2388	0	0	0
T29	12376	0	0	0
T31	0	10981	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T40	0	1559	0	0
T49	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	4021702	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	11693	332	0	0
T10	1285923	18281	0	0
T11	153870	832	0	0
T12	205350	5704	0	0
T13	211238	3965	0	0
T14	0	4574	0	0
T23	407916	339	0	0
T24	432	0	0	0
T25	5456	127	0	0
T26	1615738	8145	0	0
T27	2388	0	0	0
T29	12376	0	0	0
T31	0	10981	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T40	0	1559	0	0
T49	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	3	0	974
T50	164283	1	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	195274	0	0	1
T54	599363	0	0	1
T55	511140	0	0	1
T56	979828	0	0	1
T57	1839	0	0	1
T58	650162	0	0	1
T59	26468	0	0	1
T60	129752	0	0	1
T61	1445	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	656704324	0	0
T1	255290	255233	0	0
T2	334499	334439	0	0
T3	647750	647243	0	0
T4	39187	38713	0	0
T5	327111	326690	0	0
T6	42709	42188	0	0
T7	789	690	0	0
T8	230867	230365	0	0
T9	16212	11398	0	0
T10	1285923	804509	0	0
T11	153870	76668	0	0
T12	102675	1016683	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815787834	4021702	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	11693	332	0	0
T10	1285923	18281	0	0
T11	153870	832	0	0
T12	205350	5704	0	0
T13	211238	3965	0	0
T14	0	4574	0	0
T23	407916	339	0	0
T24	432	0	0	0
T25	5456	127	0	0
T26	1615738	8145	0	0
T27	2388	0	0	0
T29	12376	0	0	0
T31	0	10981	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T40	0	1559	0	0
T49	0	64	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T12
1	0	Covered	T9,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Unreachable
1	1	Covered	T9,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T10,T12
0	0	1	Unreachable
0	0	0	Covered	T9,T10,T12

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	157570848	29749651	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	157570848	684458	0	0
GntImpliesValid_A	157570848	684458	0	0
GrantKnown_A	157570848	29749651	0	0
IdxKnown_A	157570848	29749651	0	0
IndexIsCorrect_A	157570848	684458	0	0
LockArbDecision_A	157570848	0	0	0
NoReadyValidNoGrant_A	157570848	0	0	0
ReadyAndValidImplyGrant_A	157570848	684458	0	0
ReqAndReadyImplyGrant_A	157570848	684458	0	0
ReqImpliesValid_A	157570848	684458	0	0
ReqStaysHighUntilGranted0_M	157570848	0	0	0
RoundRobin_A	157570848	0	0	0
ValidKnown_A	157570848	29749651	0	0
gen_data_port_assertion.DataFlow_A	157570848	684458	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	29749651	0	0
T9	4519	4296	0	0
T10	475014	41200	0	0
T11	76935	0	0	0
T12	102675	105744	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	684458	0	0
T9	4519	231	0	0
T10	475014	2054	0	0
T11	76935	0	0	0
T12	102675	4655	0	0
T13	105619	3965	0	0
T14	0	4574	0	0
T23	203958	0	0	0
T24	216	0	0	0
T25	2728	127	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	3799	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T49	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	684458	0	0
T9	4519	231	0	0
T10	475014	2054	0	0
T11	76935	0	0	0
T12	102675	4655	0	0
T13	105619	3965	0	0
T14	0	4574	0	0
T23	203958	0	0	0
T24	216	0	0	0
T25	2728	127	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	3799	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T49	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	29749651	0	0
T9	4519	4296	0	0
T10	475014	41200	0	0
T11	76935	0	0	0
T12	102675	105744	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	29749651	0	0
T9	4519	4296	0	0
T10	475014	41200	0	0
T11	76935	0	0	0
T12	102675	105744	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	684458	0	0
T9	4519	231	0	0
T10	475014	2054	0	0
T11	76935	0	0	0
T12	102675	4655	0	0
T13	105619	3965	0	0
T14	0	4574	0	0
T23	203958	0	0	0
T24	216	0	0	0
T25	2728	127	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	3799	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T49	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	684458	0	0
T9	4519	231	0	0
T10	475014	2054	0	0
T11	76935	0	0	0
T12	102675	4655	0	0
T13	105619	3965	0	0
T14	0	4574	0	0
T23	203958	0	0	0
T24	216	0	0	0
T25	2728	127	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	3799	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T49	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	684458	0	0
T9	4519	231	0	0
T10	475014	2054	0	0
T11	76935	0	0	0
T12	102675	4655	0	0
T13	105619	3965	0	0
T14	0	4574	0	0
T23	203958	0	0	0
T24	216	0	0	0
T25	2728	127	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	3799	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T49	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	684458	0	0
T9	4519	231	0	0
T10	475014	2054	0	0
T11	76935	0	0	0
T12	102675	4655	0	0
T13	105619	3965	0	0
T14	0	4574	0	0
T23	203958	0	0	0
T24	216	0	0	0
T25	2728	127	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	3799	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T49	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	29749651	0	0
T9	4519	4296	0	0
T10	475014	41200	0	0
T11	76935	0	0	0
T12	102675	105744	0	0
T13	105619	102352	0	0
T14	0	107424	0	0
T23	203958	0	0	0
T24	216	216	0	0
T25	2728	2728	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	143568	0	0
T32	0	119920	0	0
T33	0	90984	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	684458	0	0
T9	4519	231	0	0
T10	475014	2054	0	0
T11	76935	0	0	0
T12	102675	4655	0	0
T13	105619	3965	0	0
T14	0	4574	0	0
T23	203958	0	0	0
T24	216	0	0	0
T25	2728	127	0	0
T26	807869	0	0	0
T27	1194	0	0	0
T31	0	3799	0	0
T32	0	3165	0	0
T33	0	4156	0	0
T49	0	64	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T23

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T23
1	0	Covered	T10,T12,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T10,T12,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T12,T23
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	157570848	126396920	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	157570848	950541	0	0
GntImpliesValid_A	157570848	950541	0	0
GrantKnown_A	157570848	126396920	0	0
IdxKnown_A	157570848	126396920	0	0
IndexIsCorrect_A	157570848	950541	0	0
LockArbDecision_A	157570848	0	0	0
NoReadyValidNoGrant_A	157570848	0	0	0
ReadyAndValidImplyGrant_A	157570848	950541	0	0
ReqAndReadyImplyGrant_A	157570848	950541	0	0
ReqImpliesValid_A	157570848	950541	0	0
ReqStaysHighUntilGranted0_M	157570848	0	0	0
RoundRobin_A	157570848	0	0	0
ValidKnown_A	157570848	126396920	0	0
gen_data_port_assertion.DataFlow_A	157570848	950541	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	126396920	0	0
T1	62894	62894	0	0
T2	47376	47376	0	0
T3	160843	160386	0	0
T4	16152	15768	0	0
T5	107874	107504	0	0
T6	20852	20416	0	0
T8	54249	53846	0	0
T9	4519	0	0	0
T10	475014	427423	0	0
T11	76935	76668	0	0
T12	0	910939	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	950541	0	0
T10	475014	4853	0	0
T11	76935	0	0	0
T12	102675	1049	0	0
T13	105619	0	0	0
T23	203958	339	0	0
T24	216	0	0	0
T25	2728	0	0	0
T26	807869	8145	0	0
T27	1194	0	0	0
T29	12376	0	0	0
T31	0	7182	0	0
T40	0	1559	0	0
T41	0	3885	0	0
T62	0	4688	0	0
T63	0	520	0	0
T64	0	2578	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	950541	0	0
T10	475014	4853	0	0
T11	76935	0	0	0
T12	102675	1049	0	0
T13	105619	0	0	0
T23	203958	339	0	0
T24	216	0	0	0
T25	2728	0	0	0
T26	807869	8145	0	0
T27	1194	0	0	0
T29	12376	0	0	0
T31	0	7182	0	0
T40	0	1559	0	0
T41	0	3885	0	0
T62	0	4688	0	0
T63	0	520	0	0
T64	0	2578	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	126396920	0	0
T1	62894	62894	0	0
T2	47376	47376	0	0
T3	160843	160386	0	0
T4	16152	15768	0	0
T5	107874	107504	0	0
T6	20852	20416	0	0
T8	54249	53846	0	0
T9	4519	0	0	0
T10	475014	427423	0	0
T11	76935	76668	0	0
T12	0	910939	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	126396920	0	0
T1	62894	62894	0	0
T2	47376	47376	0	0
T3	160843	160386	0	0
T4	16152	15768	0	0
T5	107874	107504	0	0
T6	20852	20416	0	0
T8	54249	53846	0	0
T9	4519	0	0	0
T10	475014	427423	0	0
T11	76935	76668	0	0
T12	0	910939	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	950541	0	0
T10	475014	4853	0	0
T11	76935	0	0	0
T12	102675	1049	0	0
T13	105619	0	0	0
T23	203958	339	0	0
T24	216	0	0	0
T25	2728	0	0	0
T26	807869	8145	0	0
T27	1194	0	0	0
T29	12376	0	0	0
T31	0	7182	0	0
T40	0	1559	0	0
T41	0	3885	0	0
T62	0	4688	0	0
T63	0	520	0	0
T64	0	2578	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	950541	0	0
T10	475014	4853	0	0
T11	76935	0	0	0
T12	102675	1049	0	0
T13	105619	0	0	0
T23	203958	339	0	0
T24	216	0	0	0
T25	2728	0	0	0
T26	807869	8145	0	0
T27	1194	0	0	0
T29	12376	0	0	0
T31	0	7182	0	0
T40	0	1559	0	0
T41	0	3885	0	0
T62	0	4688	0	0
T63	0	520	0	0
T64	0	2578	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	950541	0	0
T10	475014	4853	0	0
T11	76935	0	0	0
T12	102675	1049	0	0
T13	105619	0	0	0
T23	203958	339	0	0
T24	216	0	0	0
T25	2728	0	0	0
T26	807869	8145	0	0
T27	1194	0	0	0
T29	12376	0	0	0
T31	0	7182	0	0
T40	0	1559	0	0
T41	0	3885	0	0
T62	0	4688	0	0
T63	0	520	0	0
T64	0	2578	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	950541	0	0
T10	475014	4853	0	0
T11	76935	0	0	0
T12	102675	1049	0	0
T13	105619	0	0	0
T23	203958	339	0	0
T24	216	0	0	0
T25	2728	0	0	0
T26	807869	8145	0	0
T27	1194	0	0	0
T29	12376	0	0	0
T31	0	7182	0	0
T40	0	1559	0	0
T41	0	3885	0	0
T62	0	4688	0	0
T63	0	520	0	0
T64	0	2578	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	126396920	0	0
T1	62894	62894	0	0
T2	47376	47376	0	0
T3	160843	160386	0	0
T4	16152	15768	0	0
T5	107874	107504	0	0
T6	20852	20416	0	0
T8	54249	53846	0	0
T9	4519	0	0	0
T10	475014	427423	0	0
T11	76935	76668	0	0
T12	0	910939	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157570848	950541	0	0
T10	475014	4853	0	0
T11	76935	0	0	0
T12	102675	1049	0	0
T13	105619	0	0	0
T23	203958	339	0	0
T24	216	0	0	0
T25	2728	0	0	0
T26	807869	8145	0	0
T27	1194	0	0	0
T29	12376	0	0	0
T31	0	7182	0	0
T40	0	1559	0	0
T41	0	3885	0	0
T62	0	4688	0	0
T63	0	520	0	0
T64	0	2578	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	500646138	500557753	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	500646138	2386703	0	0
GntImpliesValid_A	500646138	2386703	0	0
GrantKnown_A	500646138	500557753	0	0
IdxKnown_A	500646138	500557753	0	0
IndexIsCorrect_A	500646138	2386703	0	0
LockArbDecision_A	500646138	0	0	0
NoReadyValidNoGrant_A	500646138	0	0	0
ReadyAndValidImplyGrant_A	500646138	2386703	0	0
ReqAndReadyImplyGrant_A	500646138	2386703	0	0
ReqImpliesValid_A	500646138	2386703	0	0
ReqStaysHighUntilGranted0_M	500646138	0	0	0
RoundRobin_A	500646138	3	0	974
ValidKnown_A	500646138	500557753	0	0
gen_data_port_assertion.DataFlow_A	500646138	2386703	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	500557753	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	2386703	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	101	0	0
T10	335895	11374	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	2386703	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	101	0	0
T10	335895	11374	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	500557753	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	500557753	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	2386703	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	101	0	0
T10	335895	11374	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	2386703	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	101	0	0
T10	335895	11374	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	2386703	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	101	0	0
T10	335895	11374	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	2386703	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	101	0	0
T10	335895	11374	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	3	0	974
T50	164283	1	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	195274	0	0	1
T54	599363	0	0	1
T55	511140	0	0	1
T56	979828	0	0	1
T57	1839	0	0	1
T58	650162	0	0	1
T59	26468	0	0	1
T60	129752	0	0	1
T61	1445	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	500557753	0	0
T1	192396	192339	0	0
T2	287123	287063	0	0
T3	486907	486857	0	0
T4	23035	22945	0	0
T5	219237	219186	0	0
T6	21857	21772	0	0
T7	789	690	0	0
T8	176618	176519	0	0
T9	7174	7102	0	0
T10	335895	335886	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500646138	2386703	0	0
T1	192396	832	0	0
T2	287123	832	0	0
T3	486907	832	0	0
T4	23035	832	0	0
T5	219237	832	0	0
T6	21857	832	0	0
T7	789	0	0	0
T8	176618	832	0	0
T9	7174	101	0	0
T10	335895	11374	0	0
T11	0	832	0	0