Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3863458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4503200

1

T1

12552

T2

877

T4

2650

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4658358	1			T1	1920		T2	4		T3	55
values[0x0]	1852410	1			T1	5704		T2	433		T4	455
values[0x1]	1855890	1			T1	5754		T2	447		T4	438

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2743373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5623285

1

T1

12744

T2

879

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31015	1			T1	54		T2	6		T4	18
valid_sources[0x01]	31563	1			T1	37		T2	4		T4	16
valid_sources[0x02]	34557	1			T1	37		T2	5		T4	20
valid_sources[0x03]	29927	1			T1	71		T2	2		T4	21
valid_sources[0x04]	36008	1			T1	41		T4	19		T6	30
valid_sources[0x05]	30717	1			T1	25		T2	7		T4	25
valid_sources[0x06]	33990	1			T1	65		T2	2		T4	5
valid_sources[0x07]	31513	1			T1	53		T2	4		T4	21
valid_sources[0x08]	32366	1			T1	58		T2	5		T4	10
valid_sources[0x09]	27466	1			T1	41		T2	3		T4	16
valid_sources[0x0a]	30976	1			T1	40		T2	2		T4	13
valid_sources[0x0b]	31333	1			T1	64		T2	2		T4	28
valid_sources[0x0c]	34216	1			T1	38		T2	4		T3	1
valid_sources[0x0d]	32186	1			T1	47		T2	3		T4	5
valid_sources[0x0e]	33470	1			T1	59		T2	1		T4	26
valid_sources[0x0f]	29390	1			T1	55		T2	4		T4	21
valid_sources[0x10]	32712	1			T1	57		T2	5		T4	12
valid_sources[0x11]	31555	1			T1	26		T2	3		T4	10
valid_sources[0x12]	32914	1			T1	41		T2	4		T4	20
valid_sources[0x13]	29946	1			T1	50		T2	1		T4	13
valid_sources[0x14]	35706	1			T1	57		T2	6		T4	22
valid_sources[0x15]	30281	1			T1	62		T2	5		T3	1
valid_sources[0x16]	28779	1			T1	64		T2	5		T4	14
valid_sources[0x17]	33468	1			T1	48		T2	2		T4	8
valid_sources[0x18]	30802	1			T1	56		T2	6		T4	15
valid_sources[0x19]	32898	1			T1	32		T2	5		T4	33
valid_sources[0x1a]	33750	1			T1	49		T2	4		T4	28
valid_sources[0x1b]	33982	1			T1	50		T2	3		T4	11
valid_sources[0x1c]	33407	1			T1	43		T2	10		T4	30
valid_sources[0x1d]	29322	1			T1	55		T2	4		T4	8
valid_sources[0x1e]	30494	1			T1	41		T2	5		T4	22
valid_sources[0x1f]	32582	1			T1	71		T2	7		T4	17
valid_sources[0x20]	31915	1			T1	54		T2	2		T4	13
valid_sources[0x21]	32050	1			T1	51		T2	5		T3	1
valid_sources[0x22]	30769	1			T1	82		T2	2		T4	9
valid_sources[0x23]	33341	1			T1	38		T2	5		T4	21
valid_sources[0x24]	29812	1			T1	47		T2	2		T4	18
valid_sources[0x25]	29121	1			T1	46		T2	2		T4	18
valid_sources[0x26]	30240	1			T1	43		T2	3		T4	14
valid_sources[0x27]	29673	1			T1	56		T2	2		T4	22
valid_sources[0x28]	32997	1			T1	50		T2	4		T4	28
valid_sources[0x29]	34191	1			T1	50		T2	7		T4	17
valid_sources[0x2a]	33748	1			T1	37		T2	3		T4	16
valid_sources[0x2b]	31399	1			T1	44		T2	3		T4	10
valid_sources[0x2c]	34388	1			T1	42		T2	1		T4	17
valid_sources[0x2d]	31993	1			T1	61		T2	6		T4	18
valid_sources[0x2e]	30731	1			T1	65		T2	1		T4	15
valid_sources[0x2f]	31074	1			T1	62		T2	3		T3	1
valid_sources[0x30]	31334	1			T1	58		T2	3		T3	1
valid_sources[0x31]	30368	1			T1	50		T2	5		T4	14
valid_sources[0x32]	39149	1			T1	56		T2	5		T4	25
valid_sources[0x33]	36286	1			T1	34		T2	7		T3	2
valid_sources[0x34]	27474	1			T1	44		T4	36		T6	37
valid_sources[0x35]	30836	1			T1	45		T2	4		T3	2
valid_sources[0x36]	29984	1			T1	57		T2	6		T4	11
valid_sources[0x37]	31368	1			T1	49		T2	7		T4	13
valid_sources[0x38]	31220	1			T1	66		T2	4		T4	39
valid_sources[0x39]	30623	1			T1	52		T2	6		T4	18
valid_sources[0x3a]	42491	1			T1	58		T2	1		T4	29
valid_sources[0x3b]	31743	1			T1	45		T2	5		T4	15
valid_sources[0x3c]	30355	1			T1	51		T2	2		T4	11
valid_sources[0x3d]	34414	1			T1	50		T2	2		T3	1
valid_sources[0x3e]	35085	1			T1	61		T2	7		T3	1
valid_sources[0x3f]	32933	1			T1	56		T2	2		T4	4
valid_sources[0x40]	29306	1			T1	69		T2	4		T4	19
valid_sources[0x41]	30021	1			T1	53		T2	2		T4	21
valid_sources[0x42]	35140	1			T1	79		T2	7		T3	1
valid_sources[0x43]	29494	1			T1	72		T2	4		T3	5
valid_sources[0x44]	28684	1			T1	59		T2	6		T4	10
valid_sources[0x45]	31574	1			T1	45		T2	2		T4	14
valid_sources[0x46]	33377	1			T1	63		T2	2		T4	32
valid_sources[0x47]	31703	1			T1	51		T2	5		T4	17
valid_sources[0x48]	32318	1			T1	49		T2	4		T4	24
valid_sources[0x49]	31429	1			T1	45		T2	6		T4	14
valid_sources[0x4a]	30323	1			T1	54		T2	10		T4	26
valid_sources[0x4b]	32346	1			T1	51		T2	5		T3	3
valid_sources[0x4c]	34868	1			T1	50		T2	1		T4	34
valid_sources[0x4d]	35384	1			T1	46		T2	3		T4	17
valid_sources[0x4e]	33288	1			T1	52		T2	2		T3	3
valid_sources[0x4f]	49993	1			T1	55		T2	2		T4	12
valid_sources[0x50]	29556	1			T1	71		T2	5		T4	16
valid_sources[0x51]	31481	1			T1	66		T2	3		T3	1
valid_sources[0x52]	31560	1			T1	59		T2	6		T4	11
valid_sources[0x53]	33985	1			T1	43		T2	5		T3	1
valid_sources[0x54]	40657	1			T1	51		T2	3		T4	9
valid_sources[0x55]	34044	1			T1	42		T2	4		T4	19
valid_sources[0x56]	29355	1			T1	43		T2	3		T4	25
valid_sources[0x57]	35315	1			T1	51		T2	5		T4	3
valid_sources[0x58]	29467	1			T1	59		T2	1		T4	21
valid_sources[0x59]	29314	1			T1	51		T2	3		T4	12
valid_sources[0x5a]	30476	1			T1	39		T2	2		T4	38
valid_sources[0x5b]	29584	1			T1	39		T2	3		T3	1
valid_sources[0x5c]	35119	1			T1	48		T4	10		T6	35
valid_sources[0x5d]	31168	1			T1	50		T2	5		T4	6
valid_sources[0x5e]	31929	1			T1	75		T2	3		T4	20
valid_sources[0x5f]	32810	1			T1	59		T2	7		T4	9
valid_sources[0x60]	31467	1			T1	65		T2	2		T4	21
valid_sources[0x61]	30131	1			T1	39		T2	4		T4	21
valid_sources[0x62]	31805	1			T1	52		T2	6		T4	13
valid_sources[0x63]	29991	1			T1	51		T2	2		T4	13
valid_sources[0x64]	31796	1			T1	56		T2	2		T3	1
valid_sources[0x65]	31173	1			T1	48		T2	6		T3	1
valid_sources[0x66]	29934	1			T1	55		T2	5		T3	1
valid_sources[0x67]	30590	1			T1	22		T2	2		T4	10
valid_sources[0x68]	29377	1			T1	37		T2	3		T4	21
valid_sources[0x69]	32958	1			T1	36		T2	1		T4	21
valid_sources[0x6a]	30953	1			T1	56		T2	7		T4	21
valid_sources[0x6b]	32178	1			T1	58		T2	6		T4	27
valid_sources[0x6c]	28102	1			T1	40		T2	2		T4	12
valid_sources[0x6d]	31001	1			T1	35		T2	2		T4	22
valid_sources[0x6e]	33425	1			T1	58		T2	5		T4	19
valid_sources[0x6f]	32350	1			T1	61		T2	4		T4	30
valid_sources[0x70]	46057	1			T1	49		T2	4		T4	5
valid_sources[0x71]	31037	1			T1	37		T2	3		T4	21
valid_sources[0x72]	31537	1			T1	42		T2	2		T3	4
valid_sources[0x73]	33193	1			T1	40		T2	4		T4	20
valid_sources[0x74]	28479	1			T1	66		T2	5		T4	16
valid_sources[0x75]	34908	1			T1	56		T2	2		T3	1
valid_sources[0x76]	32073	1			T1	42		T2	3		T4	8
valid_sources[0x77]	30146	1			T1	48		T2	4		T4	12
valid_sources[0x78]	31931	1			T1	48		T2	4		T4	16
valid_sources[0x79]	32236	1			T1	35		T2	5		T4	27
valid_sources[0x7a]	32634	1			T1	41		T2	2		T4	9
valid_sources[0x7b]	31361	1			T1	48		T2	6		T4	20
valid_sources[0x7c]	31598	1			T1	62		T2	4		T4	11
valid_sources[0x7d]	37437	1			T1	54		T2	3		T4	13
valid_sources[0x7e]	29213	1			T1	67		T2	6		T4	27
valid_sources[0x7f]	31106	1			T1	60		T2	1		T4	9
valid_sources[0x80]	31562	1			T1	61		T3	1		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1142393

1

T1

1157

T2

1

T4

1768

values[0x0]

all_enables

biggest_size

1691770

1

T1

5687

T2

432

T4

450

values[0x1]

all_enables

biggest_size

1669037

1

T1

5708

T2

444

T4

432