Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3886651

1

T1

826

T2

7

T3

55

full_word

4502451

1

T1

12552

T2

877

T4

2650

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8388682	1			T1	13378		T2	884		T3	55
auto[TlIntgErrCmd]	148	1			T100	8		T101	10		T102	9
auto[TlIntgErrData]	138	1			T100	11		T101	10		T102	7
auto[TlIntgErrBoth]	134	1			T100	11		T101	10		T102	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4660573

1

T1

1920

T2

4

T3

55

auto[1]

3728529

1

T1

11458

T2

880

T4

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3517842	1			T1	763		T2	3		T3	55
auto[TlIntgErrNone]	partial	auto[1]	368419	1			T1	63		T2	4		T4	11
auto[TlIntgErrNone]	full_word	auto[0]	1142546	1			T1	1157		T2	1		T4	1768
auto[TlIntgErrNone]	full_word	auto[1]	3359875	1			T1	11395		T2	876		T4	882
auto[TlIntgErrCmd]	partial	auto[0]	62	1			T100	2		T101	6		T102	4
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T100	4		T101	3		T102	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T102	1		T155	3		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T100	2		T101	1		T173	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T100	8		T101	4		T102	3
auto[TlIntgErrData]	partial	auto[1]	68	1			T100	3		T101	6		T102	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T170	1		T174	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T102	1		T175	1		T171	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T100	5		T101	4		T102	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T100	5		T101	6		T102	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T100	1		T169	1		T176	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T169	1		T172	1		T174	1