Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	489821412	2997890	0	0
DepthKnown_A	489821412	489687383	0	0
RvalidKnown_A	489821412	489687383	0	0
WreadyKnown_A	489821412	489687383	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	2997890	0	0
T1	868455	14980	0	0
T2	243983	1663	0	0
T3	1668	0	0	0
T4	107796	1671	0	0
T5	76277	1663	0	0
T6	468997	0	0	0
T7	394016	14139	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	8316	0	0
T11	0	4990	0	0
T12	0	832	0	0
T13	0	832	0	0
T56	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	489821412	3045827	0	0
DepthKnown_A	489821412	489687383	0	0
RvalidKnown_A	489821412	489687383	0	0
WreadyKnown_A	489821412	489687383	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	3045827	0	0
T1	868455	19465	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	841	0	0
T5	76277	832	0	0
T6	468997	0	0	0
T7	394016	9984	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	4992	0	0
T11	0	3328	0	0
T12	0	2487	0	0
T13	0	3634	0	0
T56	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	489821412	189825	0	0
DepthKnown_A	489821412	489687383	0	0
RvalidKnown_A	489821412	489687383	0	0
WreadyKnown_A	489821412	489687383	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	189825	0	0
T1	868455	446	0	0
T2	243983	0	0	0
T3	1668	0	0	0
T4	107796	0	0	0
T5	76277	0	0	0
T6	468997	747	0	0
T7	394016	1242	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	256	0	0
T11	0	277	0	0
T14	0	286	0	0
T29	0	303	0	0
T30	0	558	0	0
T34	0	1001	0	0
T47	0	1350	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	489821412	404689	0	0
DepthKnown_A	489821412	489687383	0	0
RvalidKnown_A	489821412	489687383	0	0
WreadyKnown_A	489821412	489687383	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	404689	0	0
T1	868455	1303	0	0
T2	243983	0	0	0
T3	1668	0	0	0
T4	107796	0	0	0
T5	76277	0	0	0
T6	468997	747	0	0
T7	394016	1241	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	256	0	0
T11	0	277	0	0
T14	0	849	0	0
T29	0	901	0	0
T30	0	2558	0	0
T34	0	1001	0	0
T47	0	6116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	489821412	6670120	0	0
DepthKnown_A	489821412	489687383	0	0
RvalidKnown_A	489821412	489687383	0	0
WreadyKnown_A	489821412	489687383	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	6670120	0	0
T1	868455	2142	0	0
T2	243983	52	0	0
T3	1668	55	0	0
T4	107796	3534	0	0
T5	76277	66	0	0
T6	468997	8056	0	0
T7	394016	10127	0	0
T8	1236	6	0	0
T9	4657	131	0	0
T10	410081	1148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	489821412	12858471	0	0
DepthKnown_A	489821412	489687383	0	0
RvalidKnown_A	489821412	489687383	0	0
WreadyKnown_A	489821412	489687383	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	12858471	0	0
T1	868455	5506	0	0
T2	243983	52	0	0
T3	1668	262	0	0
T4	107796	15334	0	0
T5	76277	66	0	0
T6	468997	8042	0	0
T7	394016	9978	0	0
T8	1236	6	0	0
T9	4657	614	0	0
T10	410081	1148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489821412	489687383	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0