Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T6,T7,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Unreachable
1	1	Covered	T6,T7,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	794933461	639742984	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	794933461	3850361	0	0
GntImpliesValid_A	794933461	3850361	0	0
GrantKnown_A	794933461	639742984	0	0
IdxKnown_A	794933461	639742984	0	0
IndexIsCorrect_A	794933461	3850361	0	0
LockArbDecision_A	794933461	0	0	0
NoReadyValidNoGrant_A	794933461	0	0	0
ReadyAndValidImplyGrant_A	794933461	3850361	0	0
ReqAndReadyImplyGrant_A	794933461	3850361	0	0
ReqImpliesValid_A	794933461	3850361	0	0
ReqStaysHighUntilGranted0_M	794933461	0	0	0
RoundRobin_A	794933461	7	0	976
ValidKnown_A	794933461	639742984	0	0
gen_data_port_assertion.DataFlow_A	794933461	3850361	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	639742984	0	0
T1	1644675	1641760	0	0
T2	284171	284114	0	0
T3	1668	1615	0	0
T4	122459	122022	0	0
T5	149009	148947	0	0
T6	642603	550201	0	0
T7	1775830	1076967	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	1157627	782563	0	0
T11	480176	238495	0	0
T12	269376	133732	0	0
T13	134064	67032	0	0
T14	467564	463040	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	3850361	0	0
T1	1644675	20140	0	0
T2	284171	832	0	0
T3	1668	0	0	0
T4	122459	832	0	0
T5	149009	832	0	0
T6	642603	5903	0	0
T7	1775830	21517	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	1157627	8470	0	0
T11	480176	7661	0	0
T12	269376	832	0	0
T13	134064	832	0	0
T14	467564	1343	0	0
T15	0	7433	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	9422	0	0
T35	0	6091	0	0
T47	0	16910	0	0
T50	13538	0	0	0
T52	0	2983	0	0
T57	0	3415	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	3850361	0	0
T1	1644675	20140	0	0
T2	284171	832	0	0
T3	1668	0	0	0
T4	122459	832	0	0
T5	149009	832	0	0
T6	642603	5903	0	0
T7	1775830	21517	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	1157627	8470	0	0
T11	480176	7661	0	0
T12	269376	832	0	0
T13	134064	832	0	0
T14	467564	1343	0	0
T15	0	7433	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	9422	0	0
T35	0	6091	0	0
T47	0	16910	0	0
T50	13538	0	0	0
T52	0	2983	0	0
T57	0	3415	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	639742984	0	0
T1	1644675	1641760	0	0
T2	284171	284114	0	0
T3	1668	1615	0	0
T4	122459	122022	0	0
T5	149009	148947	0	0
T6	642603	550201	0	0
T7	1775830	1076967	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	1157627	782563	0	0
T11	480176	238495	0	0
T12	269376	133732	0	0
T13	134064	67032	0	0
T14	467564	463040	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	639742984	0	0
T1	1644675	1641760	0	0
T2	284171	284114	0	0
T3	1668	1615	0	0
T4	122459	122022	0	0
T5	149009	148947	0	0
T6	642603	550201	0	0
T7	1775830	1076967	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	1157627	782563	0	0
T11	480176	238495	0	0
T12	269376	133732	0	0
T13	134064	67032	0	0
T14	467564	463040	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	3850361	0	0
T1	1644675	20140	0	0
T2	284171	832	0	0
T3	1668	0	0	0
T4	122459	832	0	0
T5	149009	832	0	0
T6	642603	5903	0	0
T7	1775830	21517	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	1157627	8470	0	0
T11	480176	7661	0	0
T12	269376	832	0	0
T13	134064	832	0	0
T14	467564	1343	0	0
T15	0	7433	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	9422	0	0
T35	0	6091	0	0
T47	0	16910	0	0
T50	13538	0	0	0
T52	0	2983	0	0
T57	0	3415	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	3850361	0	0
T1	1644675	20140	0	0
T2	284171	832	0	0
T3	1668	0	0	0
T4	122459	832	0	0
T5	149009	832	0	0
T6	642603	5903	0	0
T7	1775830	21517	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	1157627	8470	0	0
T11	480176	7661	0	0
T12	269376	832	0	0
T13	134064	832	0	0
T14	467564	1343	0	0
T15	0	7433	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	9422	0	0
T35	0	6091	0	0
T47	0	16910	0	0
T50	13538	0	0	0
T52	0	2983	0	0
T57	0	3415	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	3850361	0	0
T1	1644675	20140	0	0
T2	284171	832	0	0
T3	1668	0	0	0
T4	122459	832	0	0
T5	149009	832	0	0
T6	642603	5903	0	0
T7	1775830	21517	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	1157627	8470	0	0
T11	480176	7661	0	0
T12	269376	832	0	0
T13	134064	832	0	0
T14	467564	1343	0	0
T15	0	7433	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	9422	0	0
T35	0	6091	0	0
T47	0	16910	0	0
T50	13538	0	0	0
T52	0	2983	0	0
T57	0	3415	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	3850361	0	0
T1	1644675	20140	0	0
T2	284171	832	0	0
T3	1668	0	0	0
T4	122459	832	0	0
T5	149009	832	0	0
T6	642603	5903	0	0
T7	1775830	21517	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	1157627	8470	0	0
T11	480176	7661	0	0
T12	269376	832	0	0
T13	134064	832	0	0
T14	467564	1343	0	0
T15	0	7433	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	9422	0	0
T35	0	6091	0	0
T47	0	16910	0	0
T50	13538	0	0	0
T52	0	2983	0	0
T57	0	3415	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	7	0	976
T15	203460	0	0	1
T16	5645	0	0	1
T23	3026	0	0	1
T24	1359	0	0	1
T25	22895	0	0	1
T26	54804	0	0	1
T27	513472	0	0	1
T34	326645	2	0	1
T35	435248	0	0	1
T49	13253	0	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	639742984	0	0
T1	1644675	1641760	0	0
T2	284171	284114	0	0
T3	1668	1615	0	0
T4	122459	122022	0	0
T5	149009	148947	0	0
T6	642603	550201	0	0
T7	1775830	1076967	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	1157627	782563	0	0
T11	480176	238495	0	0
T12	269376	133732	0	0
T13	134064	67032	0	0
T14	467564	463040	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794933461	3850361	0	0
T1	1644675	20140	0	0
T2	284171	832	0	0
T3	1668	0	0	0
T4	122459	832	0	0
T5	149009	832	0	0
T6	642603	5903	0	0
T7	1775830	21517	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	1157627	8470	0	0
T11	480176	7661	0	0
T12	269376	832	0	0
T13	134064	832	0	0
T14	467564	1343	0	0
T15	0	7433	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	9422	0	0
T35	0	6091	0	0
T47	0	16910	0	0
T50	13538	0	0	0
T52	0	2983	0	0
T57	0	3415	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T6,T7,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Unreachable
1	1	Covered	T6,T7,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T11
0	0	1	Unreachable
0	0	0	Covered	T6,T7,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153717053	27744824	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153717053	609657	0	0
GntImpliesValid_A	153717053	609657	0	0
GrantKnown_A	153717053	27744824	0	0
IdxKnown_A	153717053	27744824	0	0
IndexIsCorrect_A	153717053	609657	0	0
LockArbDecision_A	153717053	0	0	0
NoReadyValidNoGrant_A	153717053	0	0	0
ReadyAndValidImplyGrant_A	153717053	609657	0	0
ReqAndReadyImplyGrant_A	153717053	609657	0	0
ReqImpliesValid_A	153717053	609657	0	0
ReqStaysHighUntilGranted0_M	153717053	0	0	0
RoundRobin_A	153717053	0	0	0
ValidKnown_A	153717053	27744824	0	0
gen_data_port_assertion.DataFlow_A	153717053	609657	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	27744824	0	0
T6	86803	81272	0	0
T7	690907	276608	0	0
T10	373773	0	0	0
T11	240088	72240	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	24432	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	609657	0	0
T6	86803	4082	0	0
T7	690907	4705	0	0
T10	373773	0	0	0
T11	240088	676	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	551	0	0
T15	0	5174	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	2667	0	0
T35	0	3303	0	0
T50	13538	0	0	0
T57	0	3415	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	609657	0	0
T6	86803	4082	0	0
T7	690907	4705	0	0
T10	373773	0	0	0
T11	240088	676	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	551	0	0
T15	0	5174	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	2667	0	0
T35	0	3303	0	0
T50	13538	0	0	0
T57	0	3415	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	27744824	0	0
T6	86803	81272	0	0
T7	690907	276608	0	0
T10	373773	0	0	0
T11	240088	72240	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	24432	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	27744824	0	0
T6	86803	81272	0	0
T7	690907	276608	0	0
T10	373773	0	0	0
T11	240088	72240	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	24432	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	609657	0	0
T6	86803	4082	0	0
T7	690907	4705	0	0
T10	373773	0	0	0
T11	240088	676	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	551	0	0
T15	0	5174	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	2667	0	0
T35	0	3303	0	0
T50	13538	0	0	0
T57	0	3415	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	609657	0	0
T6	86803	4082	0	0
T7	690907	4705	0	0
T10	373773	0	0	0
T11	240088	676	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	551	0	0
T15	0	5174	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	2667	0	0
T35	0	3303	0	0
T50	13538	0	0	0
T57	0	3415	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	609657	0	0
T6	86803	4082	0	0
T7	690907	4705	0	0
T10	373773	0	0	0
T11	240088	676	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	551	0	0
T15	0	5174	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	2667	0	0
T35	0	3303	0	0
T50	13538	0	0	0
T57	0	3415	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	609657	0	0
T6	86803	4082	0	0
T7	690907	4705	0	0
T10	373773	0	0	0
T11	240088	676	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	551	0	0
T15	0	5174	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	2667	0	0
T35	0	3303	0	0
T50	13538	0	0	0
T57	0	3415	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	27744824	0	0
T6	86803	81272	0	0
T7	690907	276608	0	0
T10	373773	0	0	0
T11	240088	72240	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	24432	0	0
T29	37087	35504	0	0
T30	83699	81752	0	0
T32	0	15000	0	0
T33	0	64984	0	0
T34	0	230776	0	0
T35	0	201472	0	0
T50	13538	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	609657	0	0
T6	86803	4082	0	0
T7	690907	4705	0	0
T10	373773	0	0	0
T11	240088	676	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	467564	551	0	0
T15	0	5174	0	0
T29	37087	1725	0	0
T30	83699	3206	0	0
T34	0	2667	0	0
T35	0	3303	0	0
T50	13538	0	0	0
T57	0	3415	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153717053	124586499	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153717053	898615	0	0
GntImpliesValid_A	153717053	898615	0	0
GrantKnown_A	153717053	124586499	0	0
IdxKnown_A	153717053	124586499	0	0
IndexIsCorrect_A	153717053	898615	0	0
LockArbDecision_A	153717053	0	0	0
NoReadyValidNoGrant_A	153717053	0	0	0
ReadyAndValidImplyGrant_A	153717053	898615	0	0
ReqAndReadyImplyGrant_A	153717053	898615	0	0
ReqImpliesValid_A	153717053	898615	0	0
ReqStaysHighUntilGranted0_M	153717053	0	0	0
RoundRobin_A	153717053	0	0	0
ValidKnown_A	153717053	124586499	0	0
gen_data_port_assertion.DataFlow_A	153717053	898615	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	124586499	0	0
T1	776220	773376	0	0
T2	40188	40188	0	0
T4	14663	14311	0	0
T5	72732	72732	0	0
T6	86803	0	0	0
T7	690907	406420	0	0
T10	373773	372543	0	0
T11	240088	166255	0	0
T12	134688	133732	0	0
T13	67032	67032	0	0
T14	0	438608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	898615	0	0
T1	776220	8845	0	0
T2	40188	0	0	0
T4	14663	0	0	0
T5	72732	0	0	0
T6	86803	0	0	0
T7	690907	4033	0	0
T10	373773	3213	0	0
T11	240088	3156	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	0	792	0	0
T15	0	2259	0	0
T34	0	6755	0	0
T35	0	2788	0	0
T47	0	16910	0	0
T52	0	2983	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	898615	0	0
T1	776220	8845	0	0
T2	40188	0	0	0
T4	14663	0	0	0
T5	72732	0	0	0
T6	86803	0	0	0
T7	690907	4033	0	0
T10	373773	3213	0	0
T11	240088	3156	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	0	792	0	0
T15	0	2259	0	0
T34	0	6755	0	0
T35	0	2788	0	0
T47	0	16910	0	0
T52	0	2983	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	124586499	0	0
T1	776220	773376	0	0
T2	40188	40188	0	0
T4	14663	14311	0	0
T5	72732	72732	0	0
T6	86803	0	0	0
T7	690907	406420	0	0
T10	373773	372543	0	0
T11	240088	166255	0	0
T12	134688	133732	0	0
T13	67032	67032	0	0
T14	0	438608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	124586499	0	0
T1	776220	773376	0	0
T2	40188	40188	0	0
T4	14663	14311	0	0
T5	72732	72732	0	0
T6	86803	0	0	0
T7	690907	406420	0	0
T10	373773	372543	0	0
T11	240088	166255	0	0
T12	134688	133732	0	0
T13	67032	67032	0	0
T14	0	438608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	898615	0	0
T1	776220	8845	0	0
T2	40188	0	0	0
T4	14663	0	0	0
T5	72732	0	0	0
T6	86803	0	0	0
T7	690907	4033	0	0
T10	373773	3213	0	0
T11	240088	3156	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	0	792	0	0
T15	0	2259	0	0
T34	0	6755	0	0
T35	0	2788	0	0
T47	0	16910	0	0
T52	0	2983	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	898615	0	0
T1	776220	8845	0	0
T2	40188	0	0	0
T4	14663	0	0	0
T5	72732	0	0	0
T6	86803	0	0	0
T7	690907	4033	0	0
T10	373773	3213	0	0
T11	240088	3156	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	0	792	0	0
T15	0	2259	0	0
T34	0	6755	0	0
T35	0	2788	0	0
T47	0	16910	0	0
T52	0	2983	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	898615	0	0
T1	776220	8845	0	0
T2	40188	0	0	0
T4	14663	0	0	0
T5	72732	0	0	0
T6	86803	0	0	0
T7	690907	4033	0	0
T10	373773	3213	0	0
T11	240088	3156	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	0	792	0	0
T15	0	2259	0	0
T34	0	6755	0	0
T35	0	2788	0	0
T47	0	16910	0	0
T52	0	2983	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	898615	0	0
T1	776220	8845	0	0
T2	40188	0	0	0
T4	14663	0	0	0
T5	72732	0	0	0
T6	86803	0	0	0
T7	690907	4033	0	0
T10	373773	3213	0	0
T11	240088	3156	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	0	792	0	0
T15	0	2259	0	0
T34	0	6755	0	0
T35	0	2788	0	0
T47	0	16910	0	0
T52	0	2983	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	124586499	0	0
T1	776220	773376	0	0
T2	40188	40188	0	0
T4	14663	14311	0	0
T5	72732	72732	0	0
T6	86803	0	0	0
T7	690907	406420	0	0
T10	373773	372543	0	0
T11	240088	166255	0	0
T12	134688	133732	0	0
T13	67032	67032	0	0
T14	0	438608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153717053	898615	0	0
T1	776220	8845	0	0
T2	40188	0	0	0
T4	14663	0	0	0
T5	72732	0	0	0
T6	86803	0	0	0
T7	690907	4033	0	0
T10	373773	3213	0	0
T11	240088	3156	0	0
T12	134688	0	0	0
T13	67032	0	0	0
T14	0	792	0	0
T15	0	2259	0	0
T34	0	6755	0	0
T35	0	2788	0	0
T47	0	16910	0	0
T52	0	2983	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	487499355	487411661	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	487499355	2342089	0	0
GntImpliesValid_A	487499355	2342089	0	0
GrantKnown_A	487499355	487411661	0	0
IdxKnown_A	487499355	487411661	0	0
IndexIsCorrect_A	487499355	2342089	0	0
LockArbDecision_A	487499355	0	0	0
NoReadyValidNoGrant_A	487499355	0	0	0
ReadyAndValidImplyGrant_A	487499355	2342089	0	0
ReqAndReadyImplyGrant_A	487499355	2342089	0	0
ReqImpliesValid_A	487499355	2342089	0	0
ReqStaysHighUntilGranted0_M	487499355	0	0	0
RoundRobin_A	487499355	7	0	976
ValidKnown_A	487499355	487411661	0	0
gen_data_port_assertion.DataFlow_A	487499355	2342089	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	487411661	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	2342089	0	0
T1	868455	11295	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	832	0	0
T5	76277	832	0	0
T6	468997	1821	0	0
T7	394016	12779	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	5257	0	0
T11	0	3829	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	2342089	0	0
T1	868455	11295	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	832	0	0
T5	76277	832	0	0
T6	468997	1821	0	0
T7	394016	12779	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	5257	0	0
T11	0	3829	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	487411661	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	487411661	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	2342089	0	0
T1	868455	11295	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	832	0	0
T5	76277	832	0	0
T6	468997	1821	0	0
T7	394016	12779	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	5257	0	0
T11	0	3829	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	2342089	0	0
T1	868455	11295	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	832	0	0
T5	76277	832	0	0
T6	468997	1821	0	0
T7	394016	12779	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	5257	0	0
T11	0	3829	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	2342089	0	0
T1	868455	11295	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	832	0	0
T5	76277	832	0	0
T6	468997	1821	0	0
T7	394016	12779	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	5257	0	0
T11	0	3829	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	2342089	0	0
T1	868455	11295	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	832	0	0
T5	76277	832	0	0
T6	468997	1821	0	0
T7	394016	12779	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	5257	0	0
T11	0	3829	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	7	0	976
T15	203460	0	0	1
T16	5645	0	0	1
T23	3026	0	0	1
T24	1359	0	0	1
T25	22895	0	0	1
T26	54804	0	0	1
T27	513472	0	0	1
T34	326645	2	0	1
T35	435248	0	0	1
T49	13253	0	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	487411661	0	0
T1	868455	868384	0	0
T2	243983	243926	0	0
T3	1668	1615	0	0
T4	107796	107711	0	0
T5	76277	76215	0	0
T6	468997	468929	0	0
T7	394016	393939	0	0
T8	1236	1157	0	0
T9	4657	4560	0	0
T10	410081	410020	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487499355	2342089	0	0
T1	868455	11295	0	0
T2	243983	832	0	0
T3	1668	0	0	0
T4	107796	832	0	0
T5	76277	832	0	0
T6	468997	1821	0	0
T7	394016	12779	0	0
T8	1236	0	0	0
T9	4657	0	0	0
T10	410081	5257	0	0
T11	0	3829	0	0
T12	0	832	0	0
T13	0	832	0	0