Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4155 |
0 |
0 |
T94 |
10816 |
4 |
0 |
0 |
T95 |
5519 |
209 |
0 |
0 |
T96 |
7989 |
4 |
0 |
0 |
T97 |
14879 |
233 |
0 |
0 |
T98 |
4648 |
2 |
0 |
0 |
T99 |
3180 |
97 |
0 |
0 |
T113 |
4467 |
5 |
0 |
0 |
T114 |
5505 |
22 |
0 |
0 |
T115 |
5035 |
1 |
0 |
0 |
T116 |
4808 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2027 |
0 |
0 |
T94 |
10816 |
11 |
0 |
0 |
T98 |
4648 |
4 |
0 |
0 |
T119 |
10056 |
3 |
0 |
0 |
T122 |
103121 |
355 |
0 |
0 |
T128 |
11033 |
22 |
0 |
0 |
T129 |
270403 |
669 |
0 |
0 |
T152 |
2756 |
3 |
0 |
0 |
T153 |
21745 |
74 |
0 |
0 |
T154 |
5415 |
3 |
0 |
0 |
T155 |
90507 |
67 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2193 |
0 |
0 |
T82 |
2068 |
7 |
0 |
0 |
T94 |
10816 |
20 |
0 |
0 |
T98 |
4648 |
2 |
0 |
0 |
T119 |
10056 |
5 |
0 |
0 |
T122 |
103121 |
388 |
0 |
0 |
T128 |
11033 |
11 |
0 |
0 |
T152 |
2756 |
3 |
0 |
0 |
T153 |
21745 |
65 |
0 |
0 |
T154 |
5415 |
10 |
0 |
0 |
T155 |
90507 |
83 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2610 |
0 |
0 |
T94 |
10816 |
12 |
0 |
0 |
T98 |
4648 |
5 |
0 |
0 |
T119 |
10056 |
11 |
0 |
0 |
T122 |
103121 |
405 |
0 |
0 |
T128 |
11033 |
20 |
0 |
0 |
T129 |
270403 |
663 |
0 |
0 |
T152 |
2756 |
3 |
0 |
0 |
T153 |
21745 |
47 |
0 |
0 |
T154 |
5415 |
21 |
0 |
0 |
T155 |
90507 |
106 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
9598 |
0 |
0 |
T82 |
2068 |
4 |
0 |
0 |
T94 |
10816 |
128 |
0 |
0 |
T98 |
4648 |
6 |
0 |
0 |
T119 |
10056 |
46 |
0 |
0 |
T122 |
103121 |
355 |
0 |
0 |
T128 |
11033 |
235 |
0 |
0 |
T153 |
21745 |
96 |
0 |
0 |
T154 |
5415 |
9 |
0 |
0 |
T155 |
90507 |
982 |
0 |
0 |
T156 |
3200 |
7 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
9759 |
0 |
0 |
T82 |
2068 |
1 |
0 |
0 |
T94 |
10816 |
264 |
0 |
0 |
T98 |
4648 |
61 |
0 |
0 |
T119 |
10056 |
228 |
0 |
0 |
T122 |
103121 |
494 |
0 |
0 |
T128 |
11033 |
393 |
0 |
0 |
T153 |
21745 |
70 |
0 |
0 |
T154 |
5415 |
122 |
0 |
0 |
T155 |
90507 |
762 |
0 |
0 |
T156 |
3200 |
3 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
9368 |
0 |
0 |
T82 |
2068 |
1 |
0 |
0 |
T94 |
10816 |
256 |
0 |
0 |
T98 |
4648 |
9 |
0 |
0 |
T119 |
10056 |
130 |
0 |
0 |
T122 |
103121 |
419 |
0 |
0 |
T128 |
11033 |
234 |
0 |
0 |
T152 |
2756 |
3 |
0 |
0 |
T153 |
21745 |
57 |
0 |
0 |
T154 |
5415 |
132 |
0 |
0 |
T155 |
90507 |
973 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
9388 |
0 |
0 |
T94 |
10816 |
135 |
0 |
0 |
T98 |
4648 |
8 |
0 |
0 |
T119 |
10056 |
93 |
0 |
0 |
T122 |
103121 |
447 |
0 |
0 |
T128 |
11033 |
145 |
0 |
0 |
T152 |
2756 |
6 |
0 |
0 |
T153 |
21745 |
63 |
0 |
0 |
T154 |
5415 |
4 |
0 |
0 |
T155 |
90507 |
1004 |
0 |
0 |
T156 |
3200 |
3 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
9607 |
0 |
0 |
T94 |
10816 |
16 |
0 |
0 |
T98 |
4648 |
67 |
0 |
0 |
T119 |
10056 |
118 |
0 |
0 |
T122 |
103121 |
370 |
0 |
0 |
T128 |
11033 |
273 |
0 |
0 |
T152 |
2756 |
67 |
0 |
0 |
T153 |
21745 |
50 |
0 |
0 |
T154 |
5415 |
79 |
0 |
0 |
T155 |
90507 |
1124 |
0 |
0 |
T156 |
3200 |
9 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
10165 |
0 |
0 |
T82 |
2068 |
1 |
0 |
0 |
T94 |
10816 |
289 |
0 |
0 |
T98 |
4648 |
45 |
0 |
0 |
T119 |
10056 |
88 |
0 |
0 |
T122 |
103121 |
417 |
0 |
0 |
T152 |
2756 |
7 |
0 |
0 |
T153 |
21745 |
64 |
0 |
0 |
T154 |
5415 |
173 |
0 |
0 |
T155 |
90507 |
879 |
0 |
0 |
T156 |
3200 |
3 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
11514 |
0 |
0 |
T94 |
10816 |
249 |
0 |
0 |
T98 |
4648 |
4 |
0 |
0 |
T119 |
10056 |
156 |
0 |
0 |
T122 |
103121 |
442 |
0 |
0 |
T128 |
11033 |
380 |
0 |
0 |
T152 |
2756 |
7 |
0 |
0 |
T153 |
21745 |
73 |
0 |
0 |
T154 |
5415 |
132 |
0 |
0 |
T155 |
90507 |
1042 |
0 |
0 |
T156 |
3200 |
91 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
9436 |
0 |
0 |
T82 |
2068 |
1 |
0 |
0 |
T94 |
10816 |
127 |
0 |
0 |
T98 |
4648 |
3 |
0 |
0 |
T119 |
10056 |
141 |
0 |
0 |
T122 |
103121 |
451 |
0 |
0 |
T152 |
2756 |
7 |
0 |
0 |
T153 |
21745 |
30 |
0 |
0 |
T154 |
5415 |
10 |
0 |
0 |
T155 |
90507 |
866 |
0 |
0 |
T156 |
3200 |
4 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5616 |
0 |
0 |
T82 |
2068 |
6 |
0 |
0 |
T94 |
10816 |
61 |
0 |
0 |
T98 |
4648 |
17 |
0 |
0 |
T119 |
10056 |
72 |
0 |
0 |
T122 |
103121 |
459 |
0 |
0 |
T152 |
2756 |
30 |
0 |
0 |
T153 |
21745 |
45 |
0 |
0 |
T154 |
5415 |
66 |
0 |
0 |
T155 |
90507 |
561 |
0 |
0 |
T156 |
3200 |
24 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5383 |
0 |
0 |
T94 |
10816 |
17 |
0 |
0 |
T98 |
4648 |
2 |
0 |
0 |
T119 |
10056 |
27 |
0 |
0 |
T122 |
103121 |
498 |
0 |
0 |
T128 |
11033 |
129 |
0 |
0 |
T152 |
2756 |
5 |
0 |
0 |
T153 |
21745 |
129 |
0 |
0 |
T154 |
5415 |
7 |
0 |
0 |
T155 |
90507 |
419 |
0 |
0 |
T156 |
3200 |
6 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5125 |
0 |
0 |
T94 |
10816 |
93 |
0 |
0 |
T98 |
4648 |
25 |
0 |
0 |
T111 |
5587 |
3 |
0 |
0 |
T119 |
10056 |
45 |
0 |
0 |
T122 |
103121 |
459 |
0 |
0 |
T128 |
11033 |
65 |
0 |
0 |
T153 |
21745 |
56 |
0 |
0 |
T154 |
5415 |
16 |
0 |
0 |
T155 |
90507 |
347 |
0 |
0 |
T156 |
3200 |
25 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5350 |
0 |
0 |
T82 |
2068 |
8 |
0 |
0 |
T94 |
10816 |
11 |
0 |
0 |
T98 |
4648 |
34 |
0 |
0 |
T119 |
10056 |
49 |
0 |
0 |
T122 |
103121 |
402 |
0 |
0 |
T128 |
11033 |
151 |
0 |
0 |
T152 |
2756 |
2 |
0 |
0 |
T153 |
21745 |
84 |
0 |
0 |
T154 |
5415 |
57 |
0 |
0 |
T155 |
90507 |
490 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5354 |
0 |
0 |
T82 |
2068 |
5 |
0 |
0 |
T94 |
10816 |
96 |
0 |
0 |
T98 |
4648 |
27 |
0 |
0 |
T119 |
10056 |
52 |
0 |
0 |
T122 |
103121 |
392 |
0 |
0 |
T152 |
2756 |
29 |
0 |
0 |
T153 |
21745 |
42 |
0 |
0 |
T154 |
5415 |
8 |
0 |
0 |
T155 |
90507 |
672 |
0 |
0 |
T156 |
3200 |
1 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5412 |
0 |
0 |
T94 |
10816 |
48 |
0 |
0 |
T112 |
10010 |
2 |
0 |
0 |
T119 |
10056 |
68 |
0 |
0 |
T122 |
103121 |
460 |
0 |
0 |
T128 |
11033 |
6 |
0 |
0 |
T152 |
2756 |
26 |
0 |
0 |
T153 |
21745 |
72 |
0 |
0 |
T154 |
5415 |
52 |
0 |
0 |
T155 |
90507 |
521 |
0 |
0 |
T156 |
3200 |
31 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5329 |
0 |
0 |
T82 |
2068 |
6 |
0 |
0 |
T94 |
10816 |
21 |
0 |
0 |
T98 |
4648 |
8 |
0 |
0 |
T119 |
10056 |
79 |
0 |
0 |
T122 |
103121 |
393 |
0 |
0 |
T128 |
11033 |
129 |
0 |
0 |
T129 |
270403 |
696 |
0 |
0 |
T153 |
21745 |
88 |
0 |
0 |
T154 |
5415 |
46 |
0 |
0 |
T155 |
90507 |
585 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4814 |
0 |
0 |
T82 |
2068 |
2 |
0 |
0 |
T94 |
10816 |
10 |
0 |
0 |
T98 |
4648 |
6 |
0 |
0 |
T106 |
20497 |
2 |
0 |
0 |
T119 |
10056 |
59 |
0 |
0 |
T122 |
103121 |
368 |
0 |
0 |
T153 |
21745 |
104 |
0 |
0 |
T154 |
5415 |
65 |
0 |
0 |
T155 |
90507 |
375 |
0 |
0 |
T156 |
3200 |
38 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5080 |
0 |
0 |
T94 |
10816 |
113 |
0 |
0 |
T119 |
10056 |
30 |
0 |
0 |
T122 |
103121 |
410 |
0 |
0 |
T128 |
11033 |
57 |
0 |
0 |
T129 |
270403 |
678 |
0 |
0 |
T153 |
21745 |
48 |
0 |
0 |
T154 |
5415 |
14 |
0 |
0 |
T155 |
90507 |
519 |
0 |
0 |
T156 |
3200 |
32 |
0 |
0 |
T157 |
35985 |
193 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4788 |
0 |
0 |
T94 |
10816 |
8 |
0 |
0 |
T98 |
4648 |
4 |
0 |
0 |
T119 |
10056 |
1 |
0 |
0 |
T122 |
103121 |
451 |
0 |
0 |
T128 |
11033 |
18 |
0 |
0 |
T129 |
270403 |
630 |
0 |
0 |
T153 |
21745 |
61 |
0 |
0 |
T154 |
5415 |
10 |
0 |
0 |
T155 |
90507 |
506 |
0 |
0 |
T156 |
3200 |
36 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5064 |
0 |
0 |
T94 |
10816 |
94 |
0 |
0 |
T98 |
4648 |
11 |
0 |
0 |
T119 |
10056 |
49 |
0 |
0 |
T122 |
103121 |
409 |
0 |
0 |
T128 |
11033 |
84 |
0 |
0 |
T129 |
270403 |
649 |
0 |
0 |
T153 |
21745 |
54 |
0 |
0 |
T154 |
5415 |
5 |
0 |
0 |
T155 |
90507 |
518 |
0 |
0 |
T157 |
35985 |
161 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4673 |
0 |
0 |
T94 |
10816 |
76 |
0 |
0 |
T98 |
4648 |
26 |
0 |
0 |
T119 |
10056 |
3 |
0 |
0 |
T122 |
103121 |
445 |
0 |
0 |
T128 |
11033 |
45 |
0 |
0 |
T129 |
270403 |
653 |
0 |
0 |
T152 |
2756 |
1 |
0 |
0 |
T153 |
21745 |
54 |
0 |
0 |
T154 |
5415 |
71 |
0 |
0 |
T155 |
90507 |
380 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5541 |
0 |
0 |
T94 |
10816 |
50 |
0 |
0 |
T98 |
4648 |
14 |
0 |
0 |
T119 |
10056 |
6 |
0 |
0 |
T122 |
103121 |
350 |
0 |
0 |
T128 |
11033 |
196 |
0 |
0 |
T152 |
2756 |
25 |
0 |
0 |
T153 |
21745 |
61 |
0 |
0 |
T154 |
5415 |
68 |
0 |
0 |
T155 |
90507 |
542 |
0 |
0 |
T156 |
3200 |
27 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5195 |
0 |
0 |
T82 |
2068 |
9 |
0 |
0 |
T94 |
10816 |
11 |
0 |
0 |
T119 |
10056 |
5 |
0 |
0 |
T122 |
103121 |
443 |
0 |
0 |
T128 |
11033 |
142 |
0 |
0 |
T152 |
2756 |
7 |
0 |
0 |
T153 |
21745 |
85 |
0 |
0 |
T154 |
5415 |
5 |
0 |
0 |
T155 |
90507 |
497 |
0 |
0 |
T156 |
3200 |
25 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5305 |
0 |
0 |
T82 |
2068 |
7 |
0 |
0 |
T94 |
10816 |
18 |
0 |
0 |
T98 |
4648 |
20 |
0 |
0 |
T122 |
103121 |
428 |
0 |
0 |
T128 |
11033 |
11 |
0 |
0 |
T152 |
2756 |
5 |
0 |
0 |
T153 |
21745 |
79 |
0 |
0 |
T154 |
5415 |
12 |
0 |
0 |
T155 |
90507 |
458 |
0 |
0 |
T156 |
3200 |
3 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4930 |
0 |
0 |
T94 |
10816 |
69 |
0 |
0 |
T98 |
4648 |
28 |
0 |
0 |
T119 |
10056 |
57 |
0 |
0 |
T122 |
103121 |
383 |
0 |
0 |
T128 |
11033 |
58 |
0 |
0 |
T129 |
270403 |
676 |
0 |
0 |
T152 |
2756 |
6 |
0 |
0 |
T153 |
21745 |
82 |
0 |
0 |
T154 |
5415 |
50 |
0 |
0 |
T155 |
90507 |
607 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5010 |
0 |
0 |
T82 |
2068 |
1 |
0 |
0 |
T94 |
10816 |
58 |
0 |
0 |
T98 |
4648 |
19 |
0 |
0 |
T119 |
10056 |
32 |
0 |
0 |
T122 |
103121 |
446 |
0 |
0 |
T152 |
2756 |
3 |
0 |
0 |
T153 |
21745 |
51 |
0 |
0 |
T154 |
5415 |
15 |
0 |
0 |
T155 |
90507 |
486 |
0 |
0 |
T156 |
3200 |
26 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5274 |
0 |
0 |
T94 |
10816 |
26 |
0 |
0 |
T98 |
4648 |
11 |
0 |
0 |
T119 |
10056 |
58 |
0 |
0 |
T122 |
103121 |
455 |
0 |
0 |
T128 |
11033 |
60 |
0 |
0 |
T129 |
270403 |
626 |
0 |
0 |
T152 |
2756 |
41 |
0 |
0 |
T153 |
21745 |
51 |
0 |
0 |
T154 |
5415 |
79 |
0 |
0 |
T155 |
90507 |
542 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5205 |
0 |
0 |
T94 |
10816 |
63 |
0 |
0 |
T98 |
4648 |
8 |
0 |
0 |
T122 |
103121 |
451 |
0 |
0 |
T128 |
11033 |
103 |
0 |
0 |
T129 |
270403 |
724 |
0 |
0 |
T153 |
21745 |
91 |
0 |
0 |
T154 |
5415 |
7 |
0 |
0 |
T155 |
90507 |
326 |
0 |
0 |
T156 |
3200 |
29 |
0 |
0 |
T157 |
35985 |
359 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5149 |
0 |
0 |
T94 |
10816 |
64 |
0 |
0 |
T98 |
4648 |
3 |
0 |
0 |
T119 |
10056 |
36 |
0 |
0 |
T122 |
103121 |
432 |
0 |
0 |
T128 |
11033 |
88 |
0 |
0 |
T129 |
270403 |
634 |
0 |
0 |
T153 |
21745 |
73 |
0 |
0 |
T154 |
5415 |
12 |
0 |
0 |
T155 |
90507 |
341 |
0 |
0 |
T157 |
35985 |
426 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5364 |
0 |
0 |
T82 |
2068 |
9 |
0 |
0 |
T94 |
10816 |
43 |
0 |
0 |
T119 |
10056 |
48 |
0 |
0 |
T122 |
103121 |
475 |
0 |
0 |
T128 |
11033 |
49 |
0 |
0 |
T152 |
2756 |
1 |
0 |
0 |
T153 |
21745 |
88 |
0 |
0 |
T154 |
5415 |
12 |
0 |
0 |
T155 |
90507 |
395 |
0 |
0 |
T156 |
3200 |
19 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4926 |
0 |
0 |
T82 |
2068 |
7 |
0 |
0 |
T94 |
10816 |
84 |
0 |
0 |
T98 |
4648 |
16 |
0 |
0 |
T119 |
10056 |
73 |
0 |
0 |
T122 |
103121 |
382 |
0 |
0 |
T152 |
2756 |
6 |
0 |
0 |
T153 |
21745 |
77 |
0 |
0 |
T154 |
5415 |
9 |
0 |
0 |
T155 |
90507 |
357 |
0 |
0 |
T156 |
3200 |
1 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4854 |
0 |
0 |
T94 |
10816 |
9 |
0 |
0 |
T98 |
4648 |
27 |
0 |
0 |
T119 |
10056 |
53 |
0 |
0 |
T122 |
103121 |
384 |
0 |
0 |
T128 |
11033 |
46 |
0 |
0 |
T129 |
270403 |
729 |
0 |
0 |
T153 |
21745 |
94 |
0 |
0 |
T154 |
5415 |
3 |
0 |
0 |
T155 |
90507 |
442 |
0 |
0 |
T157 |
35985 |
254 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
5206 |
0 |
0 |
T82 |
2068 |
4 |
0 |
0 |
T94 |
10816 |
52 |
0 |
0 |
T98 |
4648 |
7 |
0 |
0 |
T119 |
10056 |
41 |
0 |
0 |
T122 |
103121 |
481 |
0 |
0 |
T128 |
11033 |
161 |
0 |
0 |
T153 |
21745 |
99 |
0 |
0 |
T154 |
5415 |
13 |
0 |
0 |
T155 |
90507 |
528 |
0 |
0 |
T156 |
3200 |
5 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2349 |
0 |
0 |
T94 |
10816 |
14 |
0 |
0 |
T98 |
4648 |
18 |
0 |
0 |
T122 |
103121 |
371 |
0 |
0 |
T128 |
11033 |
19 |
0 |
0 |
T129 |
270403 |
655 |
0 |
0 |
T152 |
2756 |
4 |
0 |
0 |
T153 |
21745 |
48 |
0 |
0 |
T154 |
5415 |
8 |
0 |
0 |
T155 |
90507 |
114 |
0 |
0 |
T157 |
35985 |
69 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2232 |
0 |
0 |
T82 |
2068 |
5 |
0 |
0 |
T94 |
10816 |
19 |
0 |
0 |
T119 |
10056 |
10 |
0 |
0 |
T122 |
103121 |
346 |
0 |
0 |
T128 |
11033 |
31 |
0 |
0 |
T129 |
270403 |
660 |
0 |
0 |
T152 |
2756 |
6 |
0 |
0 |
T153 |
21745 |
62 |
0 |
0 |
T154 |
5415 |
20 |
0 |
0 |
T155 |
90507 |
84 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2432 |
0 |
0 |
T94 |
10816 |
39 |
0 |
0 |
T98 |
4648 |
3 |
0 |
0 |
T119 |
10056 |
13 |
0 |
0 |
T122 |
103121 |
459 |
0 |
0 |
T128 |
11033 |
22 |
0 |
0 |
T129 |
270403 |
692 |
0 |
0 |
T152 |
2756 |
3 |
0 |
0 |
T153 |
21745 |
46 |
0 |
0 |
T154 |
5415 |
4 |
0 |
0 |
T155 |
90507 |
91 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2345 |
0 |
0 |
T94 |
10816 |
13 |
0 |
0 |
T98 |
4648 |
5 |
0 |
0 |
T119 |
10056 |
5 |
0 |
0 |
T122 |
103121 |
403 |
0 |
0 |
T128 |
11033 |
11 |
0 |
0 |
T129 |
270403 |
632 |
0 |
0 |
T153 |
21745 |
63 |
0 |
0 |
T154 |
5415 |
10 |
0 |
0 |
T155 |
90507 |
108 |
0 |
0 |
T156 |
3200 |
5 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2973 |
0 |
0 |
T94 |
10816 |
30 |
0 |
0 |
T98 |
4648 |
12 |
0 |
0 |
T119 |
10056 |
21 |
0 |
0 |
T122 |
103121 |
438 |
0 |
0 |
T128 |
11033 |
47 |
0 |
0 |
T152 |
2756 |
8 |
0 |
0 |
T153 |
21745 |
88 |
0 |
0 |
T154 |
5415 |
9 |
0 |
0 |
T155 |
90507 |
212 |
0 |
0 |
T156 |
3200 |
8 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
4575 |
0 |
0 |
T9 |
4657 |
19 |
0 |
0 |
T10 |
410081 |
0 |
0 |
0 |
T11 |
82225 |
0 |
0 |
0 |
T12 |
79645 |
0 |
0 |
0 |
T13 |
547001 |
0 |
0 |
0 |
T14 |
531398 |
0 |
0 |
0 |
T16 |
0 |
38 |
0 |
0 |
T21 |
0 |
37 |
0 |
0 |
T28 |
1635 |
0 |
0 |
0 |
T29 |
269210 |
0 |
0 |
0 |
T30 |
260925 |
0 |
0 |
0 |
T56 |
3229 |
0 |
0 |
0 |
T139 |
0 |
26 |
0 |
0 |
T158 |
0 |
32 |
0 |
0 |
T159 |
0 |
15 |
0 |
0 |
T160 |
0 |
18 |
0 |
0 |
T161 |
0 |
10 |
0 |
0 |
T162 |
0 |
9 |
0 |
0 |
T163 |
0 |
28 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2486 |
0 |
0 |
T94 |
10816 |
26 |
0 |
0 |
T98 |
4648 |
1 |
0 |
0 |
T119 |
10056 |
12 |
0 |
0 |
T122 |
103121 |
415 |
0 |
0 |
T128 |
11033 |
2 |
0 |
0 |
T152 |
2756 |
7 |
0 |
0 |
T153 |
21745 |
79 |
0 |
0 |
T154 |
5415 |
11 |
0 |
0 |
T155 |
90507 |
113 |
0 |
0 |
T156 |
3200 |
9 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2254 |
0 |
0 |
T82 |
2068 |
5 |
0 |
0 |
T94 |
10816 |
11 |
0 |
0 |
T98 |
4648 |
7 |
0 |
0 |
T119 |
10056 |
10 |
0 |
0 |
T122 |
103121 |
392 |
0 |
0 |
T128 |
11033 |
25 |
0 |
0 |
T152 |
2756 |
1 |
0 |
0 |
T153 |
21745 |
100 |
0 |
0 |
T154 |
5415 |
11 |
0 |
0 |
T155 |
90507 |
66 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2060 |
0 |
0 |
T94 |
10816 |
8 |
0 |
0 |
T98 |
4648 |
6 |
0 |
0 |
T119 |
10056 |
11 |
0 |
0 |
T122 |
103121 |
430 |
0 |
0 |
T128 |
11033 |
14 |
0 |
0 |
T129 |
270403 |
635 |
0 |
0 |
T152 |
2756 |
1 |
0 |
0 |
T153 |
21745 |
89 |
0 |
0 |
T154 |
5415 |
4 |
0 |
0 |
T155 |
90507 |
56 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2082 |
0 |
0 |
T94 |
10816 |
26 |
0 |
0 |
T98 |
4648 |
7 |
0 |
0 |
T119 |
10056 |
8 |
0 |
0 |
T122 |
103121 |
461 |
0 |
0 |
T128 |
11033 |
1 |
0 |
0 |
T129 |
270403 |
675 |
0 |
0 |
T152 |
2756 |
6 |
0 |
0 |
T153 |
21745 |
66 |
0 |
0 |
T154 |
5415 |
11 |
0 |
0 |
T155 |
90507 |
58 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2030 |
0 |
0 |
T82 |
2068 |
9 |
0 |
0 |
T94 |
10816 |
15 |
0 |
0 |
T98 |
4648 |
11 |
0 |
0 |
T119 |
10056 |
7 |
0 |
0 |
T122 |
103121 |
444 |
0 |
0 |
T128 |
11033 |
7 |
0 |
0 |
T152 |
2756 |
5 |
0 |
0 |
T153 |
21745 |
37 |
0 |
0 |
T154 |
5415 |
4 |
0 |
0 |
T155 |
90507 |
77 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
1977 |
0 |
0 |
T82 |
2068 |
3 |
0 |
0 |
T94 |
10816 |
14 |
0 |
0 |
T122 |
103121 |
380 |
0 |
0 |
T128 |
11033 |
6 |
0 |
0 |
T129 |
270403 |
658 |
0 |
0 |
T152 |
2756 |
6 |
0 |
0 |
T153 |
21745 |
53 |
0 |
0 |
T154 |
5415 |
11 |
0 |
0 |
T155 |
90507 |
63 |
0 |
0 |
T156 |
3200 |
8 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2810 |
0 |
0 |
T82 |
2068 |
5 |
0 |
0 |
T94 |
10816 |
49 |
0 |
0 |
T98 |
4648 |
2 |
0 |
0 |
T119 |
10056 |
8 |
0 |
0 |
T122 |
103121 |
453 |
0 |
0 |
T128 |
11033 |
23 |
0 |
0 |
T153 |
21745 |
81 |
0 |
0 |
T154 |
5415 |
11 |
0 |
0 |
T155 |
90507 |
185 |
0 |
0 |
T156 |
3200 |
6 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2098 |
0 |
0 |
T94 |
10816 |
14 |
0 |
0 |
T98 |
4648 |
5 |
0 |
0 |
T119 |
10056 |
5 |
0 |
0 |
T122 |
103121 |
391 |
0 |
0 |
T128 |
11033 |
2 |
0 |
0 |
T129 |
270403 |
669 |
0 |
0 |
T153 |
21745 |
71 |
0 |
0 |
T154 |
5415 |
8 |
0 |
0 |
T155 |
90507 |
61 |
0 |
0 |
T156 |
3200 |
7 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
3110 |
0 |
0 |
T94 |
10816 |
33 |
0 |
0 |
T98 |
4648 |
15 |
0 |
0 |
T119 |
10056 |
17 |
0 |
0 |
T122 |
103121 |
369 |
0 |
0 |
T128 |
11033 |
52 |
0 |
0 |
T129 |
270403 |
712 |
0 |
0 |
T153 |
21745 |
88 |
0 |
0 |
T154 |
5415 |
25 |
0 |
0 |
T155 |
90507 |
185 |
0 |
0 |
T156 |
3200 |
5 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2394 |
0 |
0 |
T94 |
10816 |
21 |
0 |
0 |
T119 |
10056 |
7 |
0 |
0 |
T122 |
103121 |
392 |
0 |
0 |
T128 |
11033 |
6 |
0 |
0 |
T129 |
270403 |
704 |
0 |
0 |
T152 |
2756 |
7 |
0 |
0 |
T153 |
21745 |
45 |
0 |
0 |
T154 |
5415 |
12 |
0 |
0 |
T155 |
90507 |
86 |
0 |
0 |
T156 |
3200 |
1 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2047 |
0 |
0 |
T94 |
10816 |
22 |
0 |
0 |
T98 |
4648 |
8 |
0 |
0 |
T119 |
10056 |
2 |
0 |
0 |
T122 |
103121 |
376 |
0 |
0 |
T128 |
11033 |
14 |
0 |
0 |
T129 |
270403 |
641 |
0 |
0 |
T152 |
2756 |
6 |
0 |
0 |
T153 |
21745 |
33 |
0 |
0 |
T154 |
5415 |
11 |
0 |
0 |
T155 |
90507 |
55 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2117 |
0 |
0 |
T94 |
10816 |
14 |
0 |
0 |
T106 |
20497 |
5 |
0 |
0 |
T119 |
10056 |
5 |
0 |
0 |
T122 |
103121 |
442 |
0 |
0 |
T128 |
11033 |
12 |
0 |
0 |
T129 |
270403 |
686 |
0 |
0 |
T153 |
21745 |
101 |
0 |
0 |
T154 |
5415 |
6 |
0 |
0 |
T155 |
90507 |
62 |
0 |
0 |
T156 |
3200 |
6 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2067 |
0 |
0 |
T82 |
2068 |
2 |
0 |
0 |
T94 |
10816 |
15 |
0 |
0 |
T98 |
4648 |
11 |
0 |
0 |
T119 |
10056 |
21 |
0 |
0 |
T122 |
103121 |
474 |
0 |
0 |
T128 |
11033 |
21 |
0 |
0 |
T129 |
270403 |
620 |
0 |
0 |
T153 |
21745 |
79 |
0 |
0 |
T154 |
5415 |
7 |
0 |
0 |
T155 |
90507 |
47 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2070 |
0 |
0 |
T94 |
10816 |
5 |
0 |
0 |
T98 |
4648 |
1 |
0 |
0 |
T119 |
10056 |
3 |
0 |
0 |
T122 |
103121 |
453 |
0 |
0 |
T128 |
11033 |
14 |
0 |
0 |
T129 |
270403 |
715 |
0 |
0 |
T152 |
2756 |
2 |
0 |
0 |
T153 |
21745 |
41 |
0 |
0 |
T154 |
5415 |
1 |
0 |
0 |
T155 |
90507 |
54 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2118 |
0 |
0 |
T82 |
2068 |
4 |
0 |
0 |
T94 |
10816 |
13 |
0 |
0 |
T98 |
4648 |
4 |
0 |
0 |
T106 |
20497 |
3 |
0 |
0 |
T119 |
10056 |
17 |
0 |
0 |
T122 |
103121 |
442 |
0 |
0 |
T152 |
2756 |
1 |
0 |
0 |
T153 |
21745 |
86 |
0 |
0 |
T154 |
5415 |
5 |
0 |
0 |
T155 |
90507 |
90 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
489821412 |
2038 |
0 |
0 |
T94 |
10816 |
17 |
0 |
0 |
T98 |
4648 |
7 |
0 |
0 |
T119 |
10056 |
12 |
0 |
0 |
T122 |
103121 |
367 |
0 |
0 |
T128 |
11033 |
7 |
0 |
0 |
T152 |
2756 |
2 |
0 |
0 |
T153 |
21745 |
60 |
0 |
0 |
T154 |
5415 |
9 |
0 |
0 |
T155 |
90507 |
82 |
0 |
0 |
T156 |
3200 |
1 |
0 |
0 |