Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4206204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4676990

1

T1

34

T2

1491

T3

1165

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4976371	1			T1	1		T2	1202		T3	560
values[0x0]	1951281	1			T1	21		T2	452		T3	433
values[0x1]	1955542	1			T1	22		T2	462		T3	476

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2971899	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5911295

1

T1

36

T2

1611

T3

1223

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	39169	1			T2	7		T3	5		T4	26
valid_sources[0x01]	37357	1			T3	6		T4	30		T5	73
valid_sources[0x02]	39555	1			T2	15		T3	5		T4	21
valid_sources[0x03]	33250	1			T1	1		T2	9		T3	2
valid_sources[0x04]	32110	1			T3	8		T4	14		T5	2
valid_sources[0x05]	33799	1			T2	6		T3	4		T4	20
valid_sources[0x06]	34051	1			T2	5		T3	4		T4	38
valid_sources[0x07]	38633	1			T2	10		T3	4		T4	12
valid_sources[0x08]	31990	1			T2	7		T3	5		T4	23
valid_sources[0x09]	41906	1			T2	4		T3	8		T4	10
valid_sources[0x0a]	33814	1			T2	3		T3	7		T4	23
valid_sources[0x0b]	33553	1			T2	32		T3	5		T4	11
valid_sources[0x0c]	32256	1			T2	4		T3	6		T4	19
valid_sources[0x0d]	31185	1			T2	13		T3	5		T4	24
valid_sources[0x0e]	31091	1			T2	5		T3	5		T4	15
valid_sources[0x0f]	33319	1			T2	3		T3	9		T4	5
valid_sources[0x10]	35636	1			T1	1		T2	6		T3	5
valid_sources[0x11]	33072	1			T3	4		T4	21		T5	66
valid_sources[0x12]	36080	1			T1	2		T2	6		T3	11
valid_sources[0x13]	32753	1			T2	15		T3	8		T4	26
valid_sources[0x14]	33503	1			T1	3		T2	2		T3	6
valid_sources[0x15]	36469	1			T3	4		T4	26		T5	26
valid_sources[0x16]	35054	1			T2	5		T3	7		T4	18
valid_sources[0x17]	32713	1			T2	6		T3	5		T4	14
valid_sources[0x18]	33925	1			T3	4		T4	8		T5	5
valid_sources[0x19]	31597	1			T3	14		T4	29		T6	35
valid_sources[0x1a]	35092	1			T2	16		T3	4		T4	20
valid_sources[0x1b]	33080	1			T2	10		T3	2		T4	13
valid_sources[0x1c]	32915	1			T2	4		T3	6		T4	23
valid_sources[0x1d]	32450	1			T3	7		T4	19		T5	151
valid_sources[0x1e]	33267	1			T2	12		T3	7		T4	17
valid_sources[0x1f]	32418	1			T2	1		T3	11		T4	45
valid_sources[0x20]	41803	1			T2	7		T3	3		T4	28
valid_sources[0x21]	36453	1			T2	44		T3	2		T4	19
valid_sources[0x22]	35973	1			T3	6		T4	17		T5	110
valid_sources[0x23]	31207	1			T2	6		T3	4		T4	12
valid_sources[0x24]	33180	1			T2	5		T3	8		T4	14
valid_sources[0x25]	35889	1			T2	33		T3	5		T4	24
valid_sources[0x26]	32453	1			T2	22		T3	2		T4	10
valid_sources[0x27]	31781	1			T2	7		T3	2		T4	14
valid_sources[0x28]	34626	1			T2	4		T3	12		T4	20
valid_sources[0x29]	32686	1			T1	1		T2	15		T3	6
valid_sources[0x2a]	35510	1			T2	17		T3	5		T4	14
valid_sources[0x2b]	33925	1			T3	9		T4	15		T5	689
valid_sources[0x2c]	37012	1			T1	2		T2	18		T3	7
valid_sources[0x2d]	32938	1			T1	1		T2	14		T3	6
valid_sources[0x2e]	36269	1			T3	6		T4	27		T5	109
valid_sources[0x2f]	35056	1			T2	25		T3	5		T4	10
valid_sources[0x30]	33786	1			T2	21		T3	2		T4	6
valid_sources[0x31]	34534	1			T2	2		T3	13		T4	16
valid_sources[0x32]	32490	1			T2	4		T3	10		T4	10
valid_sources[0x33]	36400	1			T1	2		T2	3		T3	4
valid_sources[0x34]	37144	1			T2	15		T3	3		T4	16
valid_sources[0x35]	34964	1			T2	14		T3	11		T4	23
valid_sources[0x36]	32826	1			T2	3		T3	7		T4	39
valid_sources[0x37]	33980	1			T2	5		T3	8		T4	11
valid_sources[0x38]	32882	1			T2	2		T3	3		T4	20
valid_sources[0x39]	34460	1			T2	7		T3	10		T4	20
valid_sources[0x3a]	31528	1			T2	17		T3	4		T4	35
valid_sources[0x3b]	32991	1			T1	1		T2	3		T3	3
valid_sources[0x3c]	37764	1			T2	10		T3	3		T4	52
valid_sources[0x3d]	33529	1			T2	2		T3	5		T4	22
valid_sources[0x3e]	35560	1			T2	4		T3	4		T4	6
valid_sources[0x3f]	33563	1			T2	1		T3	5		T4	16
valid_sources[0x40]	33717	1			T2	1		T3	8		T4	48
valid_sources[0x41]	33430	1			T3	11		T4	21		T5	247
valid_sources[0x42]	36518	1			T2	16		T3	3		T4	24
valid_sources[0x43]	35885	1			T3	8		T4	15		T5	95
valid_sources[0x44]	32945	1			T2	4		T3	6		T4	20
valid_sources[0x45]	33596	1			T2	1		T3	3		T4	12
valid_sources[0x46]	32808	1			T2	2		T3	6		T4	39
valid_sources[0x47]	33728	1			T2	9		T3	7		T4	12
valid_sources[0x48]	35086	1			T2	1		T3	7		T4	29
valid_sources[0x49]	35967	1			T1	1		T2	16		T3	3
valid_sources[0x4a]	32716	1			T3	5		T4	19		T5	111
valid_sources[0x4b]	32387	1			T3	8		T4	23		T5	44
valid_sources[0x4c]	33631	1			T2	2		T3	4		T4	29
valid_sources[0x4d]	44704	1			T2	3		T3	4		T4	25
valid_sources[0x4e]	35734	1			T2	7		T3	10		T4	20
valid_sources[0x4f]	35607	1			T1	2		T2	8		T3	6
valid_sources[0x50]	35819	1			T2	9		T3	5		T4	21
valid_sources[0x51]	39502	1			T2	5		T3	6		T4	25
valid_sources[0x52]	30335	1			T1	1		T2	25		T3	6
valid_sources[0x53]	34117	1			T2	5		T3	5		T4	35
valid_sources[0x54]	32478	1			T2	2		T3	3		T4	16
valid_sources[0x55]	32437	1			T2	7		T3	9		T4	14
valid_sources[0x56]	34358	1			T3	5		T4	21		T5	237
valid_sources[0x57]	32480	1			T2	5		T3	4		T4	24
valid_sources[0x58]	31966	1			T3	8		T4	12		T5	131
valid_sources[0x59]	34819	1			T2	1		T3	5		T4	4
valid_sources[0x5a]	33250	1			T2	4		T3	5		T4	3
valid_sources[0x5b]	32632	1			T2	7		T3	9		T4	13
valid_sources[0x5c]	30530	1			T1	1		T2	1		T3	4
valid_sources[0x5d]	30622	1			T2	5		T3	8		T4	7
valid_sources[0x5e]	33191	1			T2	5		T3	9		T4	31
valid_sources[0x5f]	35752	1			T2	1		T3	4		T4	28
valid_sources[0x60]	34506	1			T2	36		T3	7		T4	21
valid_sources[0x61]	33684	1			T1	2		T2	23		T3	7
valid_sources[0x62]	34745	1			T2	13		T3	4		T4	21
valid_sources[0x63]	33493	1			T3	7		T4	27		T5	83
valid_sources[0x64]	35684	1			T2	14		T3	7		T4	10
valid_sources[0x65]	34232	1			T2	3		T3	5		T4	8
valid_sources[0x66]	33168	1			T2	2		T3	6		T4	22
valid_sources[0x67]	36069	1			T2	15		T3	5		T4	18
valid_sources[0x68]	34929	1			T3	4		T4	22		T5	105
valid_sources[0x69]	39061	1			T2	1		T3	5		T4	26
valid_sources[0x6a]	35748	1			T3	7		T4	22		T5	120
valid_sources[0x6b]	33908	1			T2	13		T3	8		T4	16
valid_sources[0x6c]	31667	1			T2	6		T3	10		T4	13
valid_sources[0x6d]	33710	1			T2	14		T3	9		T4	9
valid_sources[0x6e]	31588	1			T3	7		T4	25		T5	47
valid_sources[0x6f]	34398	1			T2	19		T3	7		T4	7
valid_sources[0x70]	33141	1			T2	21		T3	5		T4	28
valid_sources[0x71]	33375	1			T2	3		T3	3		T4	23
valid_sources[0x72]	35691	1			T2	9		T3	8		T4	29
valid_sources[0x73]	34467	1			T2	9		T3	12		T4	32
valid_sources[0x74]	46481	1			T2	9		T3	6		T4	32
valid_sources[0x75]	36636	1			T2	3		T3	3		T4	36
valid_sources[0x76]	36155	1			T3	4		T4	20		T6	7
valid_sources[0x77]	31665	1			T2	3		T3	5		T4	9
valid_sources[0x78]	32637	1			T2	5		T3	8		T4	31
valid_sources[0x79]	33166	1			T2	3		T3	6		T4	29
valid_sources[0x7a]	34315	1			T1	1		T2	18		T3	5
valid_sources[0x7b]	32776	1			T3	3		T4	15		T6	23
valid_sources[0x7c]	36012	1			T2	11		T3	3		T4	28
valid_sources[0x7d]	36976	1			T2	2		T3	7		T4	33
valid_sources[0x7e]	32986	1			T2	17		T3	3		T4	22
valid_sources[0x7f]	32943	1			T2	16		T3	2		T4	33
valid_sources[0x80]	36621	1			T3	6		T4	34		T5	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1148434

1

T2

582

T3

261

T4

2256

values[0x0]

all_enables

biggest_size

1775533

1

T1

16

T2

451

T3

432

values[0x1]

all_enables

biggest_size

1753023

1

T1

18

T2

458

T3

472