Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4223966

1

T1

10

T2

625

T3

304

full_word

4675974

1

T1

34

T2

1491

T3

1165

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8899500	1			T1	44		T2	2116		T3	1469
auto[TlIntgErrCmd]	134	1			T98	2		T100	10		T104	7
auto[TlIntgErrData]	149	1			T98	6		T100	9		T104	13
auto[TlIntgErrBoth]	157	1			T98	2		T100	11		T104	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4977783

1

T1

1

T2

1202

T3

560

auto[1]

3922157

1

T1

43

T2

914

T3

909

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3829052	1			T1	1		T2	620		T3	299
auto[TlIntgErrNone]	partial	auto[1]	394507	1			T1	9		T2	5		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1148556	1			T2	582		T3	261		T4	2256
auto[TlIntgErrNone]	full_word	auto[1]	3527385	1			T1	34		T2	909		T3	904
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T98	2		T100	1		T111	6
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T100	8		T104	7		T111	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T100	1		T173	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T111	1		T174	1		T145	1
auto[TlIntgErrData]	partial	auto[0]	70	1			T98	2		T100	6		T104	7
auto[TlIntgErrData]	partial	auto[1]	68	1			T98	3		T100	3		T104	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T174	1		T170	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T98	1		T104	1		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T98	1		T100	4		T104	6
auto[TlIntgErrBoth]	partial	auto[1]	89	1			T98	1		T100	6		T104	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T100	1		T175	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T176	1		T170	2		T177	1