Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T13
1	0	Covered	T5,T7,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T5,T7,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	815416232	660925733	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	815416232	3882182	0	0
GntImpliesValid_A	815416232	3882182	0	0
GrantKnown_A	815416232	660925733	0	0
IdxKnown_A	815416232	660925733	0	0
IndexIsCorrect_A	815416232	3882182	0	0
LockArbDecision_A	815416232	0	0	0
NoReadyValidNoGrant_A	815416232	0	0	0
ReadyAndValidImplyGrant_A	815416232	3882182	0	0
ReqAndReadyImplyGrant_A	815416232	3882182	0	0
ReqImpliesValid_A	815416232	3882182	0	0
ReqStaysHighUntilGranted0_M	815416232	0	0	0
RoundRobin_A	815416232	2	0	976
ValidKnown_A	815416232	660925733	0	0
gen_data_port_assertion.DataFlow_A	815416232	3882182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	660925733	0	0
T1	10224	10157	0	0
T2	47470	39403	0	0
T3	133547	79515	0	0
T4	136475	119037	0	0
T5	636117	552621	0	0
T6	632631	365895	0	0
T7	1419830	952618	0	0
T8	199698	178156	0	0
T9	1282	1205	0	0
T10	8892	7222	0	0
T11	44162	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	3882182	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	636117	23128	0	0
T6	632631	5324	0	0
T7	1419830	7148	0	0
T8	199698	1286	0	0
T9	1282	0	0	0
T10	8892	136	0	0
T11	69116	832	0	0
T12	211452	832	0	0
T13	962396	5976	0	0
T14	44670	0	0	0
T16	0	2241	0	0
T17	0	3539	0	0
T27	1472	67	0	0
T29	0	9653	0	0
T30	0	13027	0	0
T37	0	9081	0	0
T45	0	3517	0	0
T51	0	5277	0	0
T53	0	14822	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	3882182	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	636117	23128	0	0
T6	632631	5324	0	0
T7	1419830	7148	0	0
T8	199698	1286	0	0
T9	1282	0	0	0
T10	8892	136	0	0
T11	69116	832	0	0
T12	211452	832	0	0
T13	962396	5976	0	0
T14	44670	0	0	0
T16	0	2241	0	0
T17	0	3539	0	0
T27	1472	67	0	0
T29	0	9653	0	0
T30	0	13027	0	0
T37	0	9081	0	0
T45	0	3517	0	0
T51	0	5277	0	0
T53	0	14822	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	660925733	0	0
T1	10224	10157	0	0
T2	47470	39403	0	0
T3	133547	79515	0	0
T4	136475	119037	0	0
T5	636117	552621	0	0
T6	632631	365895	0	0
T7	1419830	952618	0	0
T8	199698	178156	0	0
T9	1282	1205	0	0
T10	8892	7222	0	0
T11	44162	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	660925733	0	0
T1	10224	10157	0	0
T2	47470	39403	0	0
T3	133547	79515	0	0
T4	136475	119037	0	0
T5	636117	552621	0	0
T6	632631	365895	0	0
T7	1419830	952618	0	0
T8	199698	178156	0	0
T9	1282	1205	0	0
T10	8892	7222	0	0
T11	44162	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	3882182	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	636117	23128	0	0
T6	632631	5324	0	0
T7	1419830	7148	0	0
T8	199698	1286	0	0
T9	1282	0	0	0
T10	8892	136	0	0
T11	69116	832	0	0
T12	211452	832	0	0
T13	962396	5976	0	0
T14	44670	0	0	0
T16	0	2241	0	0
T17	0	3539	0	0
T27	1472	67	0	0
T29	0	9653	0	0
T30	0	13027	0	0
T37	0	9081	0	0
T45	0	3517	0	0
T51	0	5277	0	0
T53	0	14822	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	3882182	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	636117	23128	0	0
T6	632631	5324	0	0
T7	1419830	7148	0	0
T8	199698	1286	0	0
T9	1282	0	0	0
T10	8892	136	0	0
T11	69116	832	0	0
T12	211452	832	0	0
T13	962396	5976	0	0
T14	44670	0	0	0
T16	0	2241	0	0
T17	0	3539	0	0
T27	1472	67	0	0
T29	0	9653	0	0
T30	0	13027	0	0
T37	0	9081	0	0
T45	0	3517	0	0
T51	0	5277	0	0
T53	0	14822	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	3882182	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	636117	23128	0	0
T6	632631	5324	0	0
T7	1419830	7148	0	0
T8	199698	1286	0	0
T9	1282	0	0	0
T10	8892	136	0	0
T11	69116	832	0	0
T12	211452	832	0	0
T13	962396	5976	0	0
T14	44670	0	0	0
T16	0	2241	0	0
T17	0	3539	0	0
T27	1472	67	0	0
T29	0	9653	0	0
T30	0	13027	0	0
T37	0	9081	0	0
T45	0	3517	0	0
T51	0	5277	0	0
T53	0	14822	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	3882182	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	636117	23128	0	0
T6	632631	5324	0	0
T7	1419830	7148	0	0
T8	199698	1286	0	0
T9	1282	0	0	0
T10	8892	136	0	0
T11	69116	832	0	0
T12	211452	832	0	0
T13	962396	5976	0	0
T14	44670	0	0	0
T16	0	2241	0	0
T17	0	3539	0	0
T27	1472	67	0	0
T29	0	9653	0	0
T30	0	13027	0	0
T37	0	9081	0	0
T45	0	3517	0	0
T51	0	5277	0	0
T53	0	14822	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	2	0	976
T57	129700	1	0	1
T58	0	1	0	0
T59	8002	0	0	1
T60	1339	0	0	1
T61	131758	0	0	1
T62	116318	0	0	1
T63	888983	0	0	1
T64	3457	0	0	1
T65	293658	0	0	1
T66	172347	0	0	1
T67	1585	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	660925733	0	0
T1	10224	10157	0	0
T2	47470	39403	0	0
T3	133547	79515	0	0
T4	136475	119037	0	0
T5	636117	552621	0	0
T6	632631	365895	0	0
T7	1419830	952618	0	0
T8	199698	178156	0	0
T9	1282	1205	0	0
T10	8892	7222	0	0
T11	44162	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815416232	3882182	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	636117	23128	0	0
T6	632631	5324	0	0
T7	1419830	7148	0	0
T8	199698	1286	0	0
T9	1282	0	0	0
T10	8892	136	0	0
T11	69116	832	0	0
T12	211452	832	0	0
T13	962396	5976	0	0
T14	44670	0	0	0
T16	0	2241	0	0
T17	0	3539	0	0
T27	1472	67	0	0
T29	0	9653	0	0
T30	0	13027	0	0
T37	0	9081	0	0
T45	0	3517	0	0
T51	0	5277	0	0
T53	0	14822	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153021886	27183786	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153021886	624764	0	0
GntImpliesValid_A	153021886	624764	0	0
GrantKnown_A	153021886	27183786	0	0
IdxKnown_A	153021886	27183786	0	0
IndexIsCorrect_A	153021886	624764	0	0
LockArbDecision_A	153021886	0	0	0
NoReadyValidNoGrant_A	153021886	0	0	0
ReadyAndValidImplyGrant_A	153021886	624764	0	0
ReqAndReadyImplyGrant_A	153021886	624764	0	0
ReqImpliesValid_A	153021886	624764	0	0
ReqStaysHighUntilGranted0_M	153021886	0	0	0
RoundRobin_A	153021886	0	0	0
ValidKnown_A	153021886	27183786	0	0
gen_data_port_assertion.DataFlow_A	153021886	624764	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	27183786	0	0
T1	1008	1008	0	0
T2	7167	0	0	0
T3	53968	0	0	0
T4	16846	0	0	0
T5	104605	23912	0	0
T6	263086	259528	0	0
T7	465272	48864	0	0
T8	20342	19240	0	0
T10	1576	1576	0	0
T11	22081	0	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	624764	0	0
T5	104605	766	0	0
T6	263086	3634	0	0
T7	465272	1309	0	0
T8	20342	880	0	0
T10	1576	95	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	0	0	0
T14	22335	0	0	0
T16	0	2233	0	0
T27	736	67	0	0
T29	0	5620	0	0
T30	0	6128	0	0
T45	0	3517	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	624764	0	0
T5	104605	766	0	0
T6	263086	3634	0	0
T7	465272	1309	0	0
T8	20342	880	0	0
T10	1576	95	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	0	0	0
T14	22335	0	0	0
T16	0	2233	0	0
T27	736	67	0	0
T29	0	5620	0	0
T30	0	6128	0	0
T45	0	3517	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	27183786	0	0
T1	1008	1008	0	0
T2	7167	0	0	0
T3	53968	0	0	0
T4	16846	0	0	0
T5	104605	23912	0	0
T6	263086	259528	0	0
T7	465272	48864	0	0
T8	20342	19240	0	0
T10	1576	1576	0	0
T11	22081	0	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	27183786	0	0
T1	1008	1008	0	0
T2	7167	0	0	0
T3	53968	0	0	0
T4	16846	0	0	0
T5	104605	23912	0	0
T6	263086	259528	0	0
T7	465272	48864	0	0
T8	20342	19240	0	0
T10	1576	1576	0	0
T11	22081	0	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	624764	0	0
T5	104605	766	0	0
T6	263086	3634	0	0
T7	465272	1309	0	0
T8	20342	880	0	0
T10	1576	95	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	0	0	0
T14	22335	0	0	0
T16	0	2233	0	0
T27	736	67	0	0
T29	0	5620	0	0
T30	0	6128	0	0
T45	0	3517	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	624764	0	0
T5	104605	766	0	0
T6	263086	3634	0	0
T7	465272	1309	0	0
T8	20342	880	0	0
T10	1576	95	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	0	0	0
T14	22335	0	0	0
T16	0	2233	0	0
T27	736	67	0	0
T29	0	5620	0	0
T30	0	6128	0	0
T45	0	3517	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	624764	0	0
T5	104605	766	0	0
T6	263086	3634	0	0
T7	465272	1309	0	0
T8	20342	880	0	0
T10	1576	95	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	0	0	0
T14	22335	0	0	0
T16	0	2233	0	0
T27	736	67	0	0
T29	0	5620	0	0
T30	0	6128	0	0
T45	0	3517	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	624764	0	0
T5	104605	766	0	0
T6	263086	3634	0	0
T7	465272	1309	0	0
T8	20342	880	0	0
T10	1576	95	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	0	0	0
T14	22335	0	0	0
T16	0	2233	0	0
T27	736	67	0	0
T29	0	5620	0	0
T30	0	6128	0	0
T45	0	3517	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	27183786	0	0
T1	1008	1008	0	0
T2	7167	0	0	0
T3	53968	0	0	0
T4	16846	0	0	0
T5	104605	23912	0	0
T6	263086	259528	0	0
T7	465272	48864	0	0
T8	20342	19240	0	0
T10	1576	1576	0	0
T11	22081	0	0	0
T27	0	736	0	0
T28	0	40136	0	0
T29	0	120144	0	0
T30	0	246232	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	624764	0	0
T5	104605	766	0	0
T6	263086	3634	0	0
T7	465272	1309	0	0
T8	20342	880	0	0
T10	1576	95	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	0	0	0
T14	22335	0	0	0
T16	0	2233	0	0
T27	736	67	0	0
T29	0	5620	0	0
T30	0	6128	0	0
T45	0	3517	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T13
1	0	Covered	T5,T7,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T5,T7,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153021886	124457859	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153021886	876459	0	0
GntImpliesValid_A	153021886	876459	0	0
GrantKnown_A	153021886	124457859	0	0
IdxKnown_A	153021886	124457859	0	0
IndexIsCorrect_A	153021886	876459	0	0
LockArbDecision_A	153021886	0	0	0
NoReadyValidNoGrant_A	153021886	0	0	0
ReadyAndValidImplyGrant_A	153021886	876459	0	0
ReqAndReadyImplyGrant_A	153021886	876459	0	0
ReqImpliesValid_A	153021886	876459	0	0
ReqStaysHighUntilGranted0_M	153021886	0	0	0
RoundRobin_A	153021886	0	0	0
ValidKnown_A	153021886	124457859	0	0
gen_data_port_assertion.DataFlow_A	153021886	876459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	124457859	0	0
T2	7167	6336	0	0
T3	53968	53968	0	0
T4	16846	16332	0	0
T5	104605	101808	0	0
T6	263086	0	0	0
T7	465272	414563	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	876459	0	0
T5	104605	9689	0	0
T6	263086	0	0	0
T7	465272	818	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	5976	0	0
T14	22335	0	0	0
T16	0	8	0	0
T17	0	3539	0	0
T27	736	0	0	0
T29	0	4033	0	0
T30	0	6899	0	0
T37	0	9081	0	0
T51	0	5277	0	0
T53	0	14822	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	876459	0	0
T5	104605	9689	0	0
T6	263086	0	0	0
T7	465272	818	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	5976	0	0
T14	22335	0	0	0
T16	0	8	0	0
T17	0	3539	0	0
T27	736	0	0	0
T29	0	4033	0	0
T30	0	6899	0	0
T37	0	9081	0	0
T51	0	5277	0	0
T53	0	14822	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	124457859	0	0
T2	7167	6336	0	0
T3	53968	53968	0	0
T4	16846	16332	0	0
T5	104605	101808	0	0
T6	263086	0	0	0
T7	465272	414563	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	124457859	0	0
T2	7167	6336	0	0
T3	53968	53968	0	0
T4	16846	16332	0	0
T5	104605	101808	0	0
T6	263086	0	0	0
T7	465272	414563	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	876459	0	0
T5	104605	9689	0	0
T6	263086	0	0	0
T7	465272	818	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	5976	0	0
T14	22335	0	0	0
T16	0	8	0	0
T17	0	3539	0	0
T27	736	0	0	0
T29	0	4033	0	0
T30	0	6899	0	0
T37	0	9081	0	0
T51	0	5277	0	0
T53	0	14822	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	876459	0	0
T5	104605	9689	0	0
T6	263086	0	0	0
T7	465272	818	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	5976	0	0
T14	22335	0	0	0
T16	0	8	0	0
T17	0	3539	0	0
T27	736	0	0	0
T29	0	4033	0	0
T30	0	6899	0	0
T37	0	9081	0	0
T51	0	5277	0	0
T53	0	14822	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	876459	0	0
T5	104605	9689	0	0
T6	263086	0	0	0
T7	465272	818	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	5976	0	0
T14	22335	0	0	0
T16	0	8	0	0
T17	0	3539	0	0
T27	736	0	0	0
T29	0	4033	0	0
T30	0	6899	0	0
T37	0	9081	0	0
T51	0	5277	0	0
T53	0	14822	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	876459	0	0
T5	104605	9689	0	0
T6	263086	0	0	0
T7	465272	818	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	5976	0	0
T14	22335	0	0	0
T16	0	8	0	0
T17	0	3539	0	0
T27	736	0	0	0
T29	0	4033	0	0
T30	0	6899	0	0
T37	0	9081	0	0
T51	0	5277	0	0
T53	0	14822	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	124457859	0	0
T2	7167	6336	0	0
T3	53968	53968	0	0
T4	16846	16332	0	0
T5	104605	101808	0	0
T6	263086	0	0	0
T7	465272	414563	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	22081	0	0
T12	105726	105726	0	0
T13	0	480235	0	0
T14	0	22144	0	0
T15	0	39344	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153021886	876459	0	0
T5	104605	9689	0	0
T6	263086	0	0	0
T7	465272	818	0	0
T8	20342	0	0	0
T10	1576	0	0	0
T11	22081	0	0	0
T12	105726	0	0	0
T13	481198	5976	0	0
T14	22335	0	0	0
T16	0	8	0	0
T17	0	3539	0	0
T27	736	0	0	0
T29	0	4033	0	0
T30	0	6899	0	0
T37	0	9081	0	0
T51	0	5277	0	0
T53	0	14822	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	509372460	509284088	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	509372460	2380959	0	0
GntImpliesValid_A	509372460	2380959	0	0
GrantKnown_A	509372460	509284088	0	0
IdxKnown_A	509372460	509284088	0	0
IndexIsCorrect_A	509372460	2380959	0	0
LockArbDecision_A	509372460	0	0	0
NoReadyValidNoGrant_A	509372460	0	0	0
ReadyAndValidImplyGrant_A	509372460	2380959	0	0
ReqAndReadyImplyGrant_A	509372460	2380959	0	0
ReqImpliesValid_A	509372460	2380959	0	0
ReqStaysHighUntilGranted0_M	509372460	0	0	0
RoundRobin_A	509372460	2	0	976
ValidKnown_A	509372460	509284088	0	0
gen_data_port_assertion.DataFlow_A	509372460	2380959	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	509284088	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2380959	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	12673	0	0
T6	106459	1690	0	0
T7	489286	5021	0	0
T8	159014	406	0	0
T9	1282	0	0	0
T10	5740	41	0	0
T11	24954	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2380959	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	12673	0	0
T6	106459	1690	0	0
T7	489286	5021	0	0
T8	159014	406	0	0
T9	1282	0	0	0
T10	5740	41	0	0
T11	24954	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	509284088	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	509284088	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2380959	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	12673	0	0
T6	106459	1690	0	0
T7	489286	5021	0	0
T8	159014	406	0	0
T9	1282	0	0	0
T10	5740	41	0	0
T11	24954	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2380959	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	12673	0	0
T6	106459	1690	0	0
T7	489286	5021	0	0
T8	159014	406	0	0
T9	1282	0	0	0
T10	5740	41	0	0
T11	24954	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2380959	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	12673	0	0
T6	106459	1690	0	0
T7	489286	5021	0	0
T8	159014	406	0	0
T9	1282	0	0	0
T10	5740	41	0	0
T11	24954	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2380959	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	12673	0	0
T6	106459	1690	0	0
T7	489286	5021	0	0
T8	159014	406	0	0
T9	1282	0	0	0
T10	5740	41	0	0
T11	24954	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2	0	976
T57	129700	1	0	1
T58	0	1	0	0
T59	8002	0	0	1
T60	1339	0	0	1
T61	131758	0	0	1
T62	116318	0	0	1
T63	888983	0	0	1
T64	3457	0	0	1
T65	293658	0	0	1
T66	172347	0	0	1
T67	1585	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	509284088	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509372460	2380959	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	12673	0	0
T6	106459	1690	0	0
T7	489286	5021	0	0
T8	159014	406	0	0
T9	1282	0	0	0
T10	5740	41	0	0
T11	24954	832	0	0
T12	0	832	0	0