Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3064 |
0 |
0 |
T99 |
14374 |
153 |
0 |
0 |
T100 |
79908 |
2 |
0 |
0 |
T101 |
10788 |
5 |
0 |
0 |
T102 |
3529 |
13 |
0 |
0 |
T103 |
14830 |
161 |
0 |
0 |
T105 |
15034 |
202 |
0 |
0 |
T106 |
14243 |
133 |
0 |
0 |
T107 |
6299 |
193 |
0 |
0 |
T114 |
2673 |
2 |
0 |
0 |
T115 |
17396 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2051 |
0 |
0 |
T101 |
10788 |
24 |
0 |
0 |
T105 |
15034 |
1 |
0 |
0 |
T115 |
17396 |
26 |
0 |
0 |
T118 |
234973 |
355 |
0 |
0 |
T119 |
4701 |
3 |
0 |
0 |
T145 |
34164 |
21 |
0 |
0 |
T146 |
10117 |
21 |
0 |
0 |
T147 |
65057 |
78 |
0 |
0 |
T148 |
34932 |
15 |
0 |
0 |
T149 |
15925 |
13 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2139 |
0 |
0 |
T101 |
10788 |
19 |
0 |
0 |
T115 |
17396 |
26 |
0 |
0 |
T118 |
234973 |
430 |
0 |
0 |
T119 |
4701 |
2 |
0 |
0 |
T145 |
34164 |
25 |
0 |
0 |
T146 |
10117 |
10 |
0 |
0 |
T147 |
65057 |
64 |
0 |
0 |
T148 |
34932 |
26 |
0 |
0 |
T149 |
15925 |
26 |
0 |
0 |
T150 |
7940 |
11 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2217 |
0 |
0 |
T101 |
10788 |
50 |
0 |
0 |
T115 |
17396 |
31 |
0 |
0 |
T118 |
234973 |
327 |
0 |
0 |
T119 |
4701 |
2 |
0 |
0 |
T145 |
34164 |
44 |
0 |
0 |
T146 |
10117 |
24 |
0 |
0 |
T147 |
65057 |
143 |
0 |
0 |
T148 |
34932 |
66 |
0 |
0 |
T149 |
15925 |
23 |
0 |
0 |
T150 |
7940 |
13 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
7467 |
0 |
0 |
T101 |
10788 |
217 |
0 |
0 |
T103 |
14830 |
6 |
0 |
0 |
T105 |
15034 |
6 |
0 |
0 |
T109 |
14275 |
8 |
0 |
0 |
T115 |
17396 |
272 |
0 |
0 |
T118 |
234973 |
444 |
0 |
0 |
T119 |
4701 |
97 |
0 |
0 |
T145 |
34164 |
346 |
0 |
0 |
T146 |
10117 |
260 |
0 |
0 |
T150 |
7940 |
141 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
7268 |
0 |
0 |
T101 |
10788 |
105 |
0 |
0 |
T115 |
17396 |
160 |
0 |
0 |
T118 |
234973 |
333 |
0 |
0 |
T119 |
4701 |
85 |
0 |
0 |
T145 |
34164 |
379 |
0 |
0 |
T146 |
10117 |
106 |
0 |
0 |
T147 |
65057 |
1126 |
0 |
0 |
T148 |
34932 |
550 |
0 |
0 |
T149 |
15925 |
361 |
0 |
0 |
T150 |
7940 |
152 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
6243 |
0 |
0 |
T101 |
10788 |
10 |
0 |
0 |
T103 |
14830 |
8 |
0 |
0 |
T115 |
17396 |
140 |
0 |
0 |
T118 |
234973 |
379 |
0 |
0 |
T119 |
4701 |
77 |
0 |
0 |
T145 |
34164 |
356 |
0 |
0 |
T146 |
10117 |
8 |
0 |
0 |
T147 |
65057 |
1331 |
0 |
0 |
T148 |
34932 |
329 |
0 |
0 |
T150 |
7940 |
59 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
6763 |
0 |
0 |
T101 |
10788 |
256 |
0 |
0 |
T115 |
17396 |
156 |
0 |
0 |
T118 |
234973 |
433 |
0 |
0 |
T119 |
4701 |
122 |
0 |
0 |
T145 |
34164 |
403 |
0 |
0 |
T146 |
10117 |
124 |
0 |
0 |
T147 |
65057 |
862 |
0 |
0 |
T148 |
34932 |
351 |
0 |
0 |
T149 |
15925 |
401 |
0 |
0 |
T150 |
7940 |
51 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
7502 |
0 |
0 |
T101 |
10788 |
152 |
0 |
0 |
T115 |
17396 |
247 |
0 |
0 |
T118 |
234973 |
439 |
0 |
0 |
T119 |
4701 |
108 |
0 |
0 |
T145 |
34164 |
218 |
0 |
0 |
T146 |
10117 |
134 |
0 |
0 |
T147 |
65057 |
1515 |
0 |
0 |
T148 |
34932 |
494 |
0 |
0 |
T149 |
15925 |
325 |
0 |
0 |
T150 |
7940 |
67 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
6865 |
0 |
0 |
T101 |
10788 |
231 |
0 |
0 |
T115 |
17396 |
375 |
0 |
0 |
T118 |
234973 |
455 |
0 |
0 |
T119 |
4701 |
4 |
0 |
0 |
T145 |
34164 |
417 |
0 |
0 |
T146 |
10117 |
248 |
0 |
0 |
T147 |
65057 |
906 |
0 |
0 |
T148 |
34932 |
387 |
0 |
0 |
T149 |
15925 |
147 |
0 |
0 |
T150 |
7940 |
136 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
6594 |
0 |
0 |
T101 |
10788 |
16 |
0 |
0 |
T115 |
17396 |
125 |
0 |
0 |
T118 |
234973 |
477 |
0 |
0 |
T119 |
4701 |
92 |
0 |
0 |
T145 |
34164 |
547 |
0 |
0 |
T146 |
10117 |
164 |
0 |
0 |
T147 |
65057 |
972 |
0 |
0 |
T148 |
34932 |
269 |
0 |
0 |
T149 |
15925 |
239 |
0 |
0 |
T150 |
7940 |
144 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
7092 |
0 |
0 |
T99 |
14374 |
3 |
0 |
0 |
T101 |
10788 |
271 |
0 |
0 |
T115 |
17396 |
266 |
0 |
0 |
T118 |
234973 |
416 |
0 |
0 |
T119 |
4701 |
107 |
0 |
0 |
T145 |
34164 |
403 |
0 |
0 |
T146 |
10117 |
105 |
0 |
0 |
T147 |
65057 |
1434 |
0 |
0 |
T148 |
34932 |
518 |
0 |
0 |
T150 |
7940 |
61 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
4112 |
0 |
0 |
T101 |
10788 |
53 |
0 |
0 |
T115 |
17396 |
135 |
0 |
0 |
T118 |
234973 |
382 |
0 |
0 |
T119 |
4701 |
48 |
0 |
0 |
T145 |
34164 |
239 |
0 |
0 |
T146 |
10117 |
97 |
0 |
0 |
T147 |
65057 |
629 |
0 |
0 |
T148 |
34932 |
78 |
0 |
0 |
T149 |
15925 |
155 |
0 |
0 |
T150 |
7940 |
16 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3983 |
0 |
0 |
T101 |
10788 |
56 |
0 |
0 |
T115 |
17396 |
98 |
0 |
0 |
T118 |
234973 |
405 |
0 |
0 |
T119 |
4701 |
54 |
0 |
0 |
T145 |
34164 |
222 |
0 |
0 |
T146 |
10117 |
48 |
0 |
0 |
T147 |
65057 |
567 |
0 |
0 |
T148 |
34932 |
118 |
0 |
0 |
T149 |
15925 |
72 |
0 |
0 |
T150 |
7940 |
55 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3531 |
0 |
0 |
T101 |
10788 |
11 |
0 |
0 |
T115 |
17396 |
91 |
0 |
0 |
T118 |
234973 |
364 |
0 |
0 |
T119 |
4701 |
65 |
0 |
0 |
T145 |
34164 |
133 |
0 |
0 |
T146 |
10117 |
48 |
0 |
0 |
T147 |
65057 |
476 |
0 |
0 |
T148 |
34932 |
187 |
0 |
0 |
T149 |
15925 |
55 |
0 |
0 |
T150 |
7940 |
40 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3983 |
0 |
0 |
T101 |
10788 |
14 |
0 |
0 |
T105 |
15034 |
5 |
0 |
0 |
T115 |
17396 |
222 |
0 |
0 |
T118 |
234973 |
390 |
0 |
0 |
T119 |
4701 |
54 |
0 |
0 |
T145 |
34164 |
126 |
0 |
0 |
T146 |
10117 |
14 |
0 |
0 |
T147 |
65057 |
448 |
0 |
0 |
T148 |
34932 |
215 |
0 |
0 |
T150 |
7940 |
50 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3779 |
0 |
0 |
T101 |
10788 |
15 |
0 |
0 |
T115 |
17396 |
116 |
0 |
0 |
T118 |
234973 |
454 |
0 |
0 |
T119 |
4701 |
2 |
0 |
0 |
T145 |
34164 |
96 |
0 |
0 |
T146 |
10117 |
66 |
0 |
0 |
T147 |
65057 |
618 |
0 |
0 |
T148 |
34932 |
143 |
0 |
0 |
T149 |
15925 |
86 |
0 |
0 |
T150 |
7940 |
12 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
4061 |
0 |
0 |
T101 |
10788 |
83 |
0 |
0 |
T115 |
17396 |
66 |
0 |
0 |
T118 |
234973 |
402 |
0 |
0 |
T119 |
4701 |
66 |
0 |
0 |
T145 |
34164 |
176 |
0 |
0 |
T146 |
10117 |
97 |
0 |
0 |
T147 |
65057 |
546 |
0 |
0 |
T148 |
34932 |
272 |
0 |
0 |
T149 |
15925 |
80 |
0 |
0 |
T150 |
7940 |
6 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3868 |
0 |
0 |
T101 |
10788 |
13 |
0 |
0 |
T115 |
17396 |
132 |
0 |
0 |
T118 |
234973 |
377 |
0 |
0 |
T119 |
4701 |
5 |
0 |
0 |
T145 |
34164 |
213 |
0 |
0 |
T146 |
10117 |
65 |
0 |
0 |
T147 |
65057 |
578 |
0 |
0 |
T148 |
34932 |
107 |
0 |
0 |
T149 |
15925 |
62 |
0 |
0 |
T150 |
7940 |
58 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3929 |
0 |
0 |
T101 |
10788 |
55 |
0 |
0 |
T115 |
17396 |
156 |
0 |
0 |
T118 |
234973 |
297 |
0 |
0 |
T119 |
4701 |
51 |
0 |
0 |
T145 |
34164 |
201 |
0 |
0 |
T146 |
10117 |
70 |
0 |
0 |
T147 |
65057 |
426 |
0 |
0 |
T148 |
34932 |
178 |
0 |
0 |
T149 |
15925 |
74 |
0 |
0 |
T150 |
7940 |
69 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
4251 |
0 |
0 |
T101 |
10788 |
17 |
0 |
0 |
T115 |
17396 |
132 |
0 |
0 |
T118 |
234973 |
454 |
0 |
0 |
T119 |
4701 |
5 |
0 |
0 |
T145 |
34164 |
78 |
0 |
0 |
T146 |
10117 |
60 |
0 |
0 |
T147 |
65057 |
498 |
0 |
0 |
T148 |
34932 |
126 |
0 |
0 |
T149 |
15925 |
134 |
0 |
0 |
T150 |
7940 |
38 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
4095 |
0 |
0 |
T101 |
10788 |
5 |
0 |
0 |
T115 |
17396 |
131 |
0 |
0 |
T118 |
234973 |
450 |
0 |
0 |
T119 |
4701 |
59 |
0 |
0 |
T145 |
34164 |
111 |
0 |
0 |
T146 |
10117 |
95 |
0 |
0 |
T147 |
65057 |
656 |
0 |
0 |
T148 |
34932 |
110 |
0 |
0 |
T149 |
15925 |
98 |
0 |
0 |
T150 |
7940 |
6 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3904 |
0 |
0 |
T101 |
10788 |
17 |
0 |
0 |
T115 |
17396 |
157 |
0 |
0 |
T118 |
234973 |
478 |
0 |
0 |
T119 |
4701 |
40 |
0 |
0 |
T145 |
34164 |
226 |
0 |
0 |
T146 |
10117 |
71 |
0 |
0 |
T147 |
65057 |
574 |
0 |
0 |
T148 |
34932 |
95 |
0 |
0 |
T149 |
15925 |
115 |
0 |
0 |
T150 |
7940 |
27 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3424 |
0 |
0 |
T101 |
10788 |
95 |
0 |
0 |
T115 |
17396 |
99 |
0 |
0 |
T118 |
234973 |
343 |
0 |
0 |
T119 |
4701 |
7 |
0 |
0 |
T145 |
34164 |
100 |
0 |
0 |
T146 |
10117 |
9 |
0 |
0 |
T147 |
65057 |
462 |
0 |
0 |
T148 |
34932 |
64 |
0 |
0 |
T149 |
15925 |
58 |
0 |
0 |
T150 |
7940 |
11 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3842 |
0 |
0 |
T101 |
10788 |
118 |
0 |
0 |
T115 |
17396 |
72 |
0 |
0 |
T118 |
234973 |
397 |
0 |
0 |
T119 |
4701 |
3 |
0 |
0 |
T145 |
34164 |
106 |
0 |
0 |
T146 |
10117 |
57 |
0 |
0 |
T147 |
65057 |
556 |
0 |
0 |
T148 |
34932 |
134 |
0 |
0 |
T149 |
15925 |
156 |
0 |
0 |
T150 |
7940 |
64 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3839 |
0 |
0 |
T101 |
10788 |
50 |
0 |
0 |
T115 |
17396 |
166 |
0 |
0 |
T118 |
234973 |
447 |
0 |
0 |
T119 |
4701 |
42 |
0 |
0 |
T145 |
34164 |
81 |
0 |
0 |
T146 |
10117 |
61 |
0 |
0 |
T147 |
65057 |
860 |
0 |
0 |
T148 |
34932 |
180 |
0 |
0 |
T149 |
15925 |
67 |
0 |
0 |
T150 |
7940 |
7 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
4298 |
0 |
0 |
T101 |
10788 |
66 |
0 |
0 |
T115 |
17396 |
184 |
0 |
0 |
T118 |
234973 |
452 |
0 |
0 |
T119 |
4701 |
5 |
0 |
0 |
T145 |
34164 |
149 |
0 |
0 |
T146 |
10117 |
53 |
0 |
0 |
T147 |
65057 |
648 |
0 |
0 |
T148 |
34932 |
126 |
0 |
0 |
T149 |
15925 |
173 |
0 |
0 |
T150 |
7940 |
29 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3830 |
0 |
0 |
T101 |
10788 |
102 |
0 |
0 |
T115 |
17396 |
73 |
0 |
0 |
T118 |
234973 |
362 |
0 |
0 |
T119 |
4701 |
1 |
0 |
0 |
T145 |
34164 |
147 |
0 |
0 |
T146 |
10117 |
18 |
0 |
0 |
T147 |
65057 |
452 |
0 |
0 |
T148 |
34932 |
145 |
0 |
0 |
T149 |
15925 |
73 |
0 |
0 |
T150 |
7940 |
54 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3882 |
0 |
0 |
T101 |
10788 |
112 |
0 |
0 |
T115 |
17396 |
109 |
0 |
0 |
T118 |
234973 |
382 |
0 |
0 |
T119 |
4701 |
54 |
0 |
0 |
T145 |
34164 |
58 |
0 |
0 |
T146 |
10117 |
54 |
0 |
0 |
T147 |
65057 |
548 |
0 |
0 |
T148 |
34932 |
180 |
0 |
0 |
T149 |
15925 |
47 |
0 |
0 |
T150 |
7940 |
44 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3541 |
0 |
0 |
T101 |
10788 |
18 |
0 |
0 |
T115 |
17396 |
90 |
0 |
0 |
T118 |
234973 |
392 |
0 |
0 |
T119 |
4701 |
19 |
0 |
0 |
T145 |
34164 |
83 |
0 |
0 |
T146 |
10117 |
42 |
0 |
0 |
T147 |
65057 |
334 |
0 |
0 |
T148 |
34932 |
151 |
0 |
0 |
T149 |
15925 |
31 |
0 |
0 |
T150 |
7940 |
32 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3667 |
0 |
0 |
T101 |
10788 |
50 |
0 |
0 |
T115 |
17396 |
95 |
0 |
0 |
T118 |
234973 |
414 |
0 |
0 |
T119 |
4701 |
3 |
0 |
0 |
T145 |
34164 |
200 |
0 |
0 |
T146 |
10117 |
72 |
0 |
0 |
T147 |
65057 |
537 |
0 |
0 |
T148 |
34932 |
134 |
0 |
0 |
T149 |
15925 |
122 |
0 |
0 |
T150 |
7940 |
15 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3737 |
0 |
0 |
T101 |
10788 |
79 |
0 |
0 |
T115 |
17396 |
141 |
0 |
0 |
T118 |
234973 |
340 |
0 |
0 |
T119 |
4701 |
6 |
0 |
0 |
T145 |
34164 |
195 |
0 |
0 |
T146 |
10117 |
9 |
0 |
0 |
T147 |
65057 |
523 |
0 |
0 |
T148 |
34932 |
115 |
0 |
0 |
T149 |
15925 |
75 |
0 |
0 |
T150 |
7940 |
45 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3800 |
0 |
0 |
T101 |
10788 |
100 |
0 |
0 |
T106 |
14243 |
1 |
0 |
0 |
T115 |
17396 |
83 |
0 |
0 |
T118 |
234973 |
404 |
0 |
0 |
T119 |
4701 |
5 |
0 |
0 |
T145 |
34164 |
176 |
0 |
0 |
T146 |
10117 |
20 |
0 |
0 |
T147 |
65057 |
568 |
0 |
0 |
T148 |
34932 |
155 |
0 |
0 |
T150 |
7940 |
31 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
4214 |
0 |
0 |
T101 |
10788 |
62 |
0 |
0 |
T115 |
17396 |
28 |
0 |
0 |
T118 |
234973 |
350 |
0 |
0 |
T119 |
4701 |
43 |
0 |
0 |
T145 |
34164 |
173 |
0 |
0 |
T146 |
10117 |
69 |
0 |
0 |
T147 |
65057 |
658 |
0 |
0 |
T148 |
34932 |
179 |
0 |
0 |
T149 |
15925 |
119 |
0 |
0 |
T150 |
7940 |
15 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3931 |
0 |
0 |
T101 |
10788 |
94 |
0 |
0 |
T109 |
14275 |
1 |
0 |
0 |
T115 |
17396 |
146 |
0 |
0 |
T118 |
234973 |
453 |
0 |
0 |
T119 |
4701 |
3 |
0 |
0 |
T145 |
34164 |
107 |
0 |
0 |
T146 |
10117 |
99 |
0 |
0 |
T147 |
65057 |
444 |
0 |
0 |
T148 |
34932 |
166 |
0 |
0 |
T150 |
7940 |
32 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3819 |
0 |
0 |
T101 |
10788 |
13 |
0 |
0 |
T109 |
14275 |
4 |
0 |
0 |
T115 |
17396 |
135 |
0 |
0 |
T118 |
234973 |
422 |
0 |
0 |
T119 |
4701 |
1 |
0 |
0 |
T145 |
34164 |
132 |
0 |
0 |
T146 |
10117 |
73 |
0 |
0 |
T147 |
65057 |
467 |
0 |
0 |
T148 |
34932 |
83 |
0 |
0 |
T150 |
7940 |
31 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2168 |
0 |
0 |
T101 |
10788 |
13 |
0 |
0 |
T109 |
14275 |
8 |
0 |
0 |
T115 |
17396 |
34 |
0 |
0 |
T118 |
234973 |
373 |
0 |
0 |
T119 |
4701 |
7 |
0 |
0 |
T145 |
34164 |
29 |
0 |
0 |
T146 |
10117 |
13 |
0 |
0 |
T147 |
65057 |
115 |
0 |
0 |
T148 |
34932 |
32 |
0 |
0 |
T150 |
7940 |
5 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2203 |
0 |
0 |
T101 |
10788 |
18 |
0 |
0 |
T115 |
17396 |
22 |
0 |
0 |
T118 |
234973 |
353 |
0 |
0 |
T119 |
4701 |
12 |
0 |
0 |
T145 |
34164 |
16 |
0 |
0 |
T146 |
10117 |
21 |
0 |
0 |
T147 |
65057 |
102 |
0 |
0 |
T148 |
34932 |
26 |
0 |
0 |
T149 |
15925 |
42 |
0 |
0 |
T150 |
7940 |
13 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2364 |
0 |
0 |
T101 |
10788 |
9 |
0 |
0 |
T115 |
17396 |
31 |
0 |
0 |
T118 |
234973 |
407 |
0 |
0 |
T119 |
4701 |
4 |
0 |
0 |
T145 |
34164 |
38 |
0 |
0 |
T146 |
10117 |
11 |
0 |
0 |
T147 |
65057 |
133 |
0 |
0 |
T148 |
34932 |
21 |
0 |
0 |
T149 |
15925 |
31 |
0 |
0 |
T150 |
7940 |
6 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2294 |
0 |
0 |
T101 |
10788 |
20 |
0 |
0 |
T115 |
17396 |
23 |
0 |
0 |
T118 |
234973 |
385 |
0 |
0 |
T145 |
34164 |
31 |
0 |
0 |
T146 |
10117 |
36 |
0 |
0 |
T147 |
65057 |
96 |
0 |
0 |
T148 |
34932 |
32 |
0 |
0 |
T149 |
15925 |
22 |
0 |
0 |
T150 |
7940 |
5 |
0 |
0 |
T151 |
13369 |
59 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2656 |
0 |
0 |
T101 |
10788 |
16 |
0 |
0 |
T115 |
17396 |
43 |
0 |
0 |
T118 |
234973 |
442 |
0 |
0 |
T119 |
4701 |
2 |
0 |
0 |
T145 |
34164 |
48 |
0 |
0 |
T146 |
10117 |
37 |
0 |
0 |
T147 |
65057 |
185 |
0 |
0 |
T148 |
34932 |
45 |
0 |
0 |
T149 |
15925 |
61 |
0 |
0 |
T150 |
7940 |
8 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
3692 |
0 |
0 |
T18 |
6860 |
35 |
0 |
0 |
T21 |
0 |
19 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T39 |
264032 |
0 |
0 |
0 |
T71 |
1262 |
0 |
0 |
0 |
T143 |
172875 |
0 |
0 |
0 |
T152 |
0 |
14 |
0 |
0 |
T153 |
0 |
20 |
0 |
0 |
T154 |
0 |
37 |
0 |
0 |
T155 |
0 |
22 |
0 |
0 |
T156 |
0 |
27 |
0 |
0 |
T157 |
0 |
48 |
0 |
0 |
T158 |
0 |
32 |
0 |
0 |
T159 |
15870 |
0 |
0 |
0 |
T160 |
121111 |
0 |
0 |
0 |
T161 |
467220 |
0 |
0 |
0 |
T162 |
8181 |
0 |
0 |
0 |
T163 |
13552 |
0 |
0 |
0 |
T164 |
25671 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2171 |
0 |
0 |
T101 |
10788 |
30 |
0 |
0 |
T115 |
17396 |
24 |
0 |
0 |
T118 |
234973 |
372 |
0 |
0 |
T119 |
4701 |
3 |
0 |
0 |
T145 |
34164 |
24 |
0 |
0 |
T146 |
10117 |
9 |
0 |
0 |
T147 |
65057 |
107 |
0 |
0 |
T148 |
34932 |
43 |
0 |
0 |
T149 |
15925 |
14 |
0 |
0 |
T150 |
7940 |
21 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2122 |
0 |
0 |
T101 |
10788 |
21 |
0 |
0 |
T115 |
17396 |
29 |
0 |
0 |
T118 |
234973 |
344 |
0 |
0 |
T119 |
4701 |
4 |
0 |
0 |
T145 |
34164 |
17 |
0 |
0 |
T146 |
10117 |
18 |
0 |
0 |
T147 |
65057 |
104 |
0 |
0 |
T148 |
34932 |
13 |
0 |
0 |
T149 |
15925 |
31 |
0 |
0 |
T150 |
7940 |
9 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2090 |
0 |
0 |
T101 |
10788 |
11 |
0 |
0 |
T115 |
17396 |
31 |
0 |
0 |
T118 |
234973 |
410 |
0 |
0 |
T119 |
4701 |
9 |
0 |
0 |
T145 |
34164 |
13 |
0 |
0 |
T146 |
10117 |
18 |
0 |
0 |
T147 |
65057 |
89 |
0 |
0 |
T148 |
34932 |
11 |
0 |
0 |
T149 |
15925 |
23 |
0 |
0 |
T150 |
7940 |
3 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2182 |
0 |
0 |
T101 |
10788 |
18 |
0 |
0 |
T109 |
14275 |
1 |
0 |
0 |
T115 |
17396 |
12 |
0 |
0 |
T118 |
234973 |
429 |
0 |
0 |
T119 |
4701 |
9 |
0 |
0 |
T145 |
34164 |
16 |
0 |
0 |
T146 |
10117 |
12 |
0 |
0 |
T147 |
65057 |
80 |
0 |
0 |
T148 |
34932 |
14 |
0 |
0 |
T150 |
7940 |
9 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
1920 |
0 |
0 |
T101 |
10788 |
18 |
0 |
0 |
T115 |
17396 |
21 |
0 |
0 |
T118 |
234973 |
404 |
0 |
0 |
T119 |
4701 |
9 |
0 |
0 |
T145 |
34164 |
5 |
0 |
0 |
T146 |
10117 |
22 |
0 |
0 |
T147 |
65057 |
81 |
0 |
0 |
T148 |
34932 |
14 |
0 |
0 |
T149 |
15925 |
18 |
0 |
0 |
T150 |
7940 |
9 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2183 |
0 |
0 |
T101 |
10788 |
28 |
0 |
0 |
T115 |
17396 |
25 |
0 |
0 |
T118 |
234973 |
369 |
0 |
0 |
T119 |
4701 |
9 |
0 |
0 |
T145 |
34164 |
30 |
0 |
0 |
T146 |
10117 |
9 |
0 |
0 |
T147 |
65057 |
99 |
0 |
0 |
T148 |
34932 |
19 |
0 |
0 |
T149 |
15925 |
27 |
0 |
0 |
T150 |
7940 |
1 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2623 |
0 |
0 |
T101 |
10788 |
27 |
0 |
0 |
T115 |
17396 |
46 |
0 |
0 |
T118 |
234973 |
366 |
0 |
0 |
T119 |
4701 |
3 |
0 |
0 |
T145 |
34164 |
50 |
0 |
0 |
T146 |
10117 |
29 |
0 |
0 |
T147 |
65057 |
179 |
0 |
0 |
T148 |
34932 |
101 |
0 |
0 |
T149 |
15925 |
18 |
0 |
0 |
T150 |
7940 |
26 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2092 |
0 |
0 |
T101 |
10788 |
15 |
0 |
0 |
T115 |
17396 |
26 |
0 |
0 |
T118 |
234973 |
367 |
0 |
0 |
T119 |
4701 |
5 |
0 |
0 |
T145 |
34164 |
3 |
0 |
0 |
T146 |
10117 |
19 |
0 |
0 |
T147 |
65057 |
80 |
0 |
0 |
T148 |
34932 |
14 |
0 |
0 |
T149 |
15925 |
29 |
0 |
0 |
T150 |
7940 |
2 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2672 |
0 |
0 |
T101 |
10788 |
34 |
0 |
0 |
T115 |
17396 |
28 |
0 |
0 |
T118 |
234973 |
427 |
0 |
0 |
T119 |
4701 |
7 |
0 |
0 |
T145 |
34164 |
75 |
0 |
0 |
T146 |
10117 |
5 |
0 |
0 |
T147 |
65057 |
220 |
0 |
0 |
T148 |
34932 |
76 |
0 |
0 |
T149 |
15925 |
44 |
0 |
0 |
T150 |
7940 |
9 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2008 |
0 |
0 |
T101 |
10788 |
3 |
0 |
0 |
T115 |
17396 |
29 |
0 |
0 |
T118 |
234973 |
347 |
0 |
0 |
T145 |
34164 |
41 |
0 |
0 |
T146 |
10117 |
13 |
0 |
0 |
T147 |
65057 |
107 |
0 |
0 |
T148 |
34932 |
18 |
0 |
0 |
T149 |
15925 |
13 |
0 |
0 |
T151 |
13369 |
40 |
0 |
0 |
T165 |
5532 |
5 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2211 |
0 |
0 |
T101 |
10788 |
9 |
0 |
0 |
T115 |
17396 |
24 |
0 |
0 |
T118 |
234973 |
392 |
0 |
0 |
T119 |
4701 |
4 |
0 |
0 |
T145 |
34164 |
27 |
0 |
0 |
T146 |
10117 |
15 |
0 |
0 |
T147 |
65057 |
82 |
0 |
0 |
T148 |
34932 |
39 |
0 |
0 |
T149 |
15925 |
18 |
0 |
0 |
T150 |
7940 |
10 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2141 |
0 |
0 |
T101 |
10788 |
12 |
0 |
0 |
T103 |
14830 |
6 |
0 |
0 |
T115 |
17396 |
24 |
0 |
0 |
T118 |
234973 |
390 |
0 |
0 |
T145 |
34164 |
34 |
0 |
0 |
T146 |
10117 |
21 |
0 |
0 |
T147 |
65057 |
71 |
0 |
0 |
T148 |
34932 |
18 |
0 |
0 |
T149 |
15925 |
34 |
0 |
0 |
T151 |
13369 |
23 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
1978 |
0 |
0 |
T101 |
10788 |
15 |
0 |
0 |
T115 |
17396 |
14 |
0 |
0 |
T118 |
234973 |
385 |
0 |
0 |
T119 |
4701 |
8 |
0 |
0 |
T145 |
34164 |
29 |
0 |
0 |
T146 |
10117 |
14 |
0 |
0 |
T147 |
65057 |
83 |
0 |
0 |
T148 |
34932 |
16 |
0 |
0 |
T149 |
15925 |
32 |
0 |
0 |
T150 |
7940 |
2 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2115 |
0 |
0 |
T101 |
10788 |
27 |
0 |
0 |
T115 |
17396 |
36 |
0 |
0 |
T118 |
234973 |
468 |
0 |
0 |
T119 |
4701 |
3 |
0 |
0 |
T145 |
34164 |
15 |
0 |
0 |
T146 |
10117 |
14 |
0 |
0 |
T147 |
65057 |
88 |
0 |
0 |
T148 |
34932 |
13 |
0 |
0 |
T149 |
15925 |
24 |
0 |
0 |
T150 |
7940 |
4 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2134 |
0 |
0 |
T101 |
10788 |
10 |
0 |
0 |
T115 |
17396 |
16 |
0 |
0 |
T118 |
234973 |
426 |
0 |
0 |
T119 |
4701 |
4 |
0 |
0 |
T145 |
34164 |
25 |
0 |
0 |
T146 |
10117 |
24 |
0 |
0 |
T147 |
65057 |
93 |
0 |
0 |
T148 |
34932 |
26 |
0 |
0 |
T149 |
15925 |
18 |
0 |
0 |
T150 |
7940 |
9 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
511844741 |
2075 |
0 |
0 |
T101 |
10788 |
14 |
0 |
0 |
T115 |
17396 |
30 |
0 |
0 |
T118 |
234973 |
405 |
0 |
0 |
T119 |
4701 |
4 |
0 |
0 |
T145 |
34164 |
23 |
0 |
0 |
T146 |
10117 |
22 |
0 |
0 |
T147 |
65057 |
52 |
0 |
0 |
T148 |
34932 |
11 |
0 |
0 |
T149 |
15925 |
26 |
0 |
0 |
T150 |
7940 |
9 |
0 |
0 |