Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3430665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4168088

1

T1

1904

T2

840

T3

877

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4116134	1			T1	2065		T2	1		T3	2
values[0x0]	1739559	1			T1	465		T2	479		T3	439
values[0x1]	1743060	1			T1	425		T2	522		T3	439

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2433229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5165524

1

T1

2129

T2

876

T3

877

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28964	1			T1	11		T2	6		T4	5
valid_sources[0x01]	26404	1			T1	8		T2	1		T3	11
valid_sources[0x02]	26566	1			T1	11		T2	6		T3	1
valid_sources[0x03]	27111	1			T1	15		T2	1		T3	5
valid_sources[0x04]	31251	1			T1	13		T3	5		T4	4
valid_sources[0x05]	30958	1			T1	9		T2	1		T3	7
valid_sources[0x06]	27561	1			T1	10		T4	3		T6	9
valid_sources[0x07]	34088	1			T1	10		T2	11		T3	1
valid_sources[0x08]	28111	1			T1	10		T3	1		T4	6
valid_sources[0x09]	28387	1			T1	12		T2	3		T4	1
valid_sources[0x0a]	26235	1			T1	13		T3	2		T4	4
valid_sources[0x0b]	30425	1			T1	12		T2	8		T3	3
valid_sources[0x0c]	28389	1			T1	15		T2	23		T4	6
valid_sources[0x0d]	26743	1			T1	13		T2	7		T4	5
valid_sources[0x0e]	28053	1			T1	8		T4	4		T6	8
valid_sources[0x0f]	25346	1			T1	14		T2	13		T3	5
valid_sources[0x10]	27738	1			T1	8		T3	7		T4	1
valid_sources[0x11]	27341	1			T1	12		T4	5		T6	17
valid_sources[0x12]	28709	1			T1	11		T2	2		T3	1
valid_sources[0x13]	32652	1			T1	7		T3	8		T4	4
valid_sources[0x14]	26521	1			T1	13		T2	3		T3	1
valid_sources[0x15]	27032	1			T1	9		T2	18		T3	2
valid_sources[0x16]	28262	1			T1	15		T3	2		T4	2
valid_sources[0x17]	34143	1			T1	7		T3	17		T4	2
valid_sources[0x18]	73322	1			T1	14		T3	4		T4	4
valid_sources[0x19]	29799	1			T1	7		T2	1		T3	3
valid_sources[0x1a]	31395	1			T1	7		T2	1		T3	8
valid_sources[0x1b]	29322	1			T1	10		T3	1		T4	5
valid_sources[0x1c]	25753	1			T1	9		T2	5		T3	4
valid_sources[0x1d]	32421	1			T1	12		T4	6		T6	13
valid_sources[0x1e]	27983	1			T1	16		T3	5		T4	1
valid_sources[0x1f]	29720	1			T1	15		T2	2		T3	2
valid_sources[0x20]	28908	1			T1	17		T3	9		T4	3
valid_sources[0x21]	26089	1			T1	9		T2	6		T4	4
valid_sources[0x22]	26833	1			T1	9		T3	4		T4	2
valid_sources[0x23]	29728	1			T1	9		T3	11		T4	5
valid_sources[0x24]	61794	1			T1	11		T3	1		T4	3
valid_sources[0x25]	28166	1			T1	12		T2	9		T3	5
valid_sources[0x26]	29212	1			T1	14		T3	2		T4	7
valid_sources[0x27]	27879	1			T1	4		T2	11		T3	3
valid_sources[0x28]	30807	1			T1	8		T2	4		T3	8
valid_sources[0x29]	28095	1			T1	14		T4	5		T6	9
valid_sources[0x2a]	27904	1			T1	8		T2	1		T3	8
valid_sources[0x2b]	31382	1			T1	13		T2	2		T3	3
valid_sources[0x2c]	30942	1			T1	12		T3	7		T4	3
valid_sources[0x2d]	30330	1			T1	10		T2	2		T3	1
valid_sources[0x2e]	27946	1			T1	14		T2	4		T3	2
valid_sources[0x2f]	27956	1			T1	13		T3	2		T4	8
valid_sources[0x30]	27953	1			T1	9		T2	24		T3	4
valid_sources[0x31]	29060	1			T1	15		T3	2		T4	3
valid_sources[0x32]	33551	1			T1	15		T3	2		T4	4
valid_sources[0x33]	27967	1			T1	4		T3	4		T6	12
valid_sources[0x34]	30561	1			T1	7		T2	6		T3	3
valid_sources[0x35]	30179	1			T1	13		T4	3		T6	8
valid_sources[0x36]	26658	1			T1	11		T2	3		T3	7
valid_sources[0x37]	26228	1			T1	11		T2	1		T3	10
valid_sources[0x38]	28017	1			T1	7		T2	14		T3	9
valid_sources[0x39]	27078	1			T1	14		T2	3		T4	5
valid_sources[0x3a]	28192	1			T1	11		T2	11		T3	6
valid_sources[0x3b]	26563	1			T1	8		T2	2		T4	5
valid_sources[0x3c]	31056	1			T1	15		T4	5		T5	293
valid_sources[0x3d]	30688	1			T1	8		T2	8		T3	1
valid_sources[0x3e]	26126	1			T1	12		T2	4		T3	6
valid_sources[0x3f]	31451	1			T1	14		T3	3		T4	4
valid_sources[0x40]	27869	1			T1	13		T2	1		T3	1
valid_sources[0x41]	30736	1			T1	9		T3	2		T4	4
valid_sources[0x42]	26116	1			T1	16		T2	11		T3	4
valid_sources[0x43]	29343	1			T1	10		T3	3		T4	2
valid_sources[0x44]	28485	1			T1	13		T3	2		T4	2
valid_sources[0x45]	32305	1			T1	11		T3	8		T4	8
valid_sources[0x46]	25788	1			T1	15		T2	13		T3	1
valid_sources[0x47]	31351	1			T1	11		T2	1		T6	12
valid_sources[0x48]	31132	1			T1	10		T3	4		T4	4
valid_sources[0x49]	25650	1			T1	10		T2	7		T3	4
valid_sources[0x4a]	32457	1			T1	7		T2	10		T3	6
valid_sources[0x4b]	25222	1			T1	14		T2	4		T3	5
valid_sources[0x4c]	29122	1			T1	10		T3	7		T4	1
valid_sources[0x4d]	26898	1			T1	14		T2	1		T4	3
valid_sources[0x4e]	32185	1			T1	10		T4	5		T6	11
valid_sources[0x4f]	33363	1			T1	8		T2	11		T3	2
valid_sources[0x50]	28136	1			T1	12		T3	2		T4	2
valid_sources[0x51]	27773	1			T1	11		T3	2		T4	3
valid_sources[0x52]	28212	1			T1	8		T2	13		T3	8
valid_sources[0x53]	29583	1			T1	12		T2	1		T3	2
valid_sources[0x54]	33248	1			T1	20		T2	14		T3	1
valid_sources[0x55]	28437	1			T1	10		T2	2		T3	1
valid_sources[0x56]	28679	1			T1	7		T2	7		T4	6
valid_sources[0x57]	27538	1			T1	18		T2	2		T3	8
valid_sources[0x58]	28502	1			T1	12		T2	10		T3	1
valid_sources[0x59]	26249	1			T1	5		T3	8		T4	4
valid_sources[0x5a]	32778	1			T1	8		T2	14		T3	2
valid_sources[0x5b]	28564	1			T1	13		T2	10		T3	2
valid_sources[0x5c]	38300	1			T1	15		T3	3		T4	4
valid_sources[0x5d]	26092	1			T1	17		T3	1		T4	7
valid_sources[0x5e]	28430	1			T1	6		T3	6		T4	5
valid_sources[0x5f]	28966	1			T1	12		T3	1		T4	1
valid_sources[0x60]	30733	1			T1	10		T2	1		T3	6
valid_sources[0x61]	28785	1			T1	13		T3	11		T4	2
valid_sources[0x62]	27022	1			T1	15		T3	3		T4	5
valid_sources[0x63]	34619	1			T1	12		T3	2		T4	2
valid_sources[0x64]	32594	1			T1	8		T2	11		T4	8
valid_sources[0x65]	29712	1			T1	13		T3	8		T4	5
valid_sources[0x66]	24492	1			T1	11		T3	3		T4	2
valid_sources[0x67]	27207	1			T1	7		T3	4		T6	6
valid_sources[0x68]	32462	1			T1	15		T2	11		T3	3
valid_sources[0x69]	26105	1			T1	10		T2	5		T4	3
valid_sources[0x6a]	26353	1			T1	10		T2	9		T3	2
valid_sources[0x6b]	29117	1			T1	9		T3	6		T4	2
valid_sources[0x6c]	28852	1			T1	8		T3	3		T4	2
valid_sources[0x6d]	26644	1			T1	14		T3	6		T4	6
valid_sources[0x6e]	26507	1			T1	10		T3	8		T4	5
valid_sources[0x6f]	28542	1			T1	12		T2	2		T3	4
valid_sources[0x70]	30405	1			T1	15		T2	9		T3	1
valid_sources[0x71]	29068	1			T1	10		T3	10		T4	2
valid_sources[0x72]	29332	1			T1	6		T2	3		T3	1
valid_sources[0x73]	28501	1			T1	11		T3	4		T4	3
valid_sources[0x74]	31569	1			T1	10		T2	3		T3	4
valid_sources[0x75]	27704	1			T1	8		T4	1		T6	7
valid_sources[0x76]	33202	1			T1	14		T3	4		T4	6
valid_sources[0x77]	27828	1			T1	11		T2	21		T3	7
valid_sources[0x78]	27185	1			T1	10		T3	1		T4	2
valid_sources[0x79]	28226	1			T1	8		T2	4		T3	1
valid_sources[0x7a]	29215	1			T1	12		T2	9		T3	4
valid_sources[0x7b]	28719	1			T1	13		T3	4		T4	7
valid_sources[0x7c]	30700	1			T1	18		T3	4		T6	13
valid_sources[0x7d]	29147	1			T1	13		T2	7		T3	7
valid_sources[0x7e]	28006	1			T1	8		T3	6		T4	2
valid_sources[0x7f]	29281	1			T1	12		T2	12		T3	5
valid_sources[0x80]	32565	1			T1	10		T2	11		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1001751

1

T1

1025

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1593216

1

T1

463

T2

398

T3

438

values[0x1]

all_enables

biggest_size

1573121

1

T1

416

T2

441

T3

438