Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3449805

1

T1

1051

T2

162

T3

3

full_word

4167145

1

T1

1904

T2

840

T3

877

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7616530	1			T1	2955		T2	1002		T3	880
auto[TlIntgErrCmd]	134	1			T97	5		T101	10		T102	6
auto[TlIntgErrData]	127	1			T97	8		T101	7		T102	7
auto[TlIntgErrBoth]	159	1			T97	7		T101	13		T102	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4117674

1

T1

2065

T2

1

T3

2

auto[1]

3499276

1

T1

890

T2

1001

T3

878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3115653	1			T1	1040		T3	1		T4	35
auto[TlIntgErrNone]	partial	auto[1]	333772	1			T1	11		T2	162		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1001846	1			T1	1025		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3165259	1			T1	879		T2	839		T3	876
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T97	1		T101	4		T102	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T97	4		T101	5		T102	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T102	1		T178	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T101	1		T117	1		T183	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T97	4		T101	2		T102	3
auto[TlIntgErrData]	partial	auto[1]	68	1			T97	3		T101	5		T102	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T184	2		T185	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	12	1			T97	1		T102	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T97	3		T101	7		T102	5
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T97	3		T101	6		T102	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T97	1		T102	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T180	2		T178	1		T183	1