Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	100.00	86.11		100.00	97.87	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T8,T12
1	1	Covered	T1,T8,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T8,T12
1	1	Covered	T1,T8,T12

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1255875735	2771	0	0
SrcPulseCheck_M	452706417	2771	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1255875735	2771	0	0
T1	220178	7	0	0
T2	1040848	0	0	0
T3	42474	0	0	0
T4	93110	0	0	0
T5	98684	0	0	0
T6	228508	0	0	0
T7	2550	0	0	0
T8	568176	28	0	0
T9	4095	0	0	0
T10	4185	0	0	0
T11	62806	0	0	0
T12	42093	7	0	0
T13	119407	5	0	0
T14	656690	7	0	0
T17	0	9	0	0
T18	0	16	0	0
T21	0	21	0	0
T24	980	0	0	0
T25	1144	0	0	0
T37	0	5	0	0
T38	0	7	0	0
T42	0	13	0	0
T43	0	9	0	0
T51	0	2	0	0
T63	0	7	0	0
T80	1068	0	0	0
T150	0	7	0	0
T151	0	3	0	0
T152	0	7	0	0
T153	0	2	0	0
T154	0	7	0	0
T155	0	7	0	0
T156	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452706417	2771	0	0
T1	42730	7	0	0
T2	259194	0	0	0
T3	4452	0	0	0
T4	278140	0	0	0
T5	39776	0	0	0
T6	164082	0	0	0
T8	460656	28	0	0
T11	59736	0	0	0
T12	58146	7	0	0
T13	447084	5	0	0
T14	799979	7	0	0
T15	44352	0	0	0
T17	0	9	0	0
T18	0	16	0	0
T21	0	21	0	0
T26	72	0	0	0
T37	0	5	0	0
T38	0	7	0	0
T39	37404	0	0	0
T42	0	13	0	0
T43	0	9	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	2	0	0
T63	0	7	0	0
T150	0	7	0	0
T151	0	3	0	0
T152	0	7	0	0
T153	0	2	0	0
T154	0	7	0	0
T155	0	7	0	0
T156	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T38
1	0	Covered	T1,T12,T38
1	1	Covered	T1,T12,T38

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T38
1	0	Covered	T1,T12,T38
1	1	Covered	T1,T12,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	418625245	164	0	0
SrcPulseCheck_M	150902139	164	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	164	0	0
T1	110089	2	0	0
T2	520424	0	0	0
T3	21237	0	0	0
T4	46555	0	0	0
T5	49342	0	0	0
T6	114254	0	0	0
T7	1275	0	0	0
T8	189392	0	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T12	0	2	0	0
T38	0	2	0	0
T63	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	164	0	0
T1	21365	2	0	0
T2	129597	0	0	0
T3	2226	0	0	0
T4	139070	0	0	0
T5	19888	0	0	0
T6	82041	0	0	0
T8	153552	0	0	0
T11	19912	0	0	0
T12	19382	2	0	0
T13	149028	0	0	0
T38	0	2	0	0
T63	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T38
1	0	Covered	T1,T12,T38
1	1	Covered	T1,T12,T38

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T38
1	0	Covered	T1,T12,T38
1	1	Covered	T1,T12,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	418625245	306	0	0
SrcPulseCheck_M	150902139	306	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	306	0	0
T1	110089	5	0	0
T2	520424	0	0	0
T3	21237	0	0	0
T4	46555	0	0	0
T5	49342	0	0	0
T6	114254	0	0	0
T7	1275	0	0	0
T8	189392	0	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T12	0	5	0	0
T38	0	5	0	0
T63	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	2	0	0
T154	0	5	0	0
T155	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	306	0	0
T1	21365	5	0	0
T2	129597	0	0	0
T3	2226	0	0	0
T4	139070	0	0	0
T5	19888	0	0	0
T6	82041	0	0	0
T8	153552	0	0	0
T11	19912	0	0	0
T12	19382	5	0	0
T13	149028	0	0	0
T38	0	5	0	0
T63	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	5	0	0
T153	0	2	0	0
T154	0	5	0	0
T155	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	418625245	2301	0	0
SrcPulseCheck_M	150902139	2301	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2301	0	0
T8	189392	28	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	62806	0	0	0
T12	42093	0	0	0
T13	119407	5	0	0
T14	656690	7	0	0
T17	0	9	0	0
T18	0	16	0	0
T21	0	21	0	0
T24	980	0	0	0
T25	1144	0	0	0
T37	0	5	0	0
T42	0	13	0	0
T43	0	9	0	0
T51	0	2	0	0
T80	1068	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	2301	0	0
T8	153552	28	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	5	0	0
T14	799979	7	0	0
T15	44352	0	0	0
T17	0	9	0	0
T18	0	16	0	0
T21	0	21	0	0
T26	72	0	0	0
T37	0	5	0	0
T39	37404	0	0	0
T42	0	13	0	0
T43	0	9	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	2	0	0