Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T13
1	0	Covered	T6,T8,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Unreachable
1	1	Covered	T6,T8,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T8,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T13
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	720429523	568114088	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	720429523	3719755	0	0
GntImpliesValid_A	720429523	3719755	0	0
GrantKnown_A	720429523	568114088	0	0
IdxKnown_A	720429523	568114088	0	0
IndexIsCorrect_A	720429523	3719755	0	0
LockArbDecision_A	720429523	0	0	0
NoReadyValidNoGrant_A	720429523	0	0	0
ReadyAndValidImplyGrant_A	720429523	3719755	0	0
ReqAndReadyImplyGrant_A	720429523	3719755	0	0
ReqImpliesValid_A	720429523	3719755	0	0
ReqStaysHighUntilGranted0_M	720429523	0	0	0
RoundRobin_A	720429523	5	0	976
ValidKnown_A	720429523	568114088	0	0
gen_data_port_assertion.DataFlow_A	720429523	3719755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	568114088	0	0
T1	131454	131388	0	0
T2	779618	643650	0	0
T3	25689	23387	0	0
T4	324695	185567	0	0
T5	89118	69170	0	0
T6	278336	193010	0	0
T7	1275	1176	0	0
T8	496496	576005	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0
T11	39824	19912	0	0
T12	38764	19382	0	0
T13	298056	147378	0	0
T14	799979	792152	0	0
T15	0	44352	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	3719755	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	196295	3014	0	0
T7	1275	0	0	0
T8	496496	34527	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	39824	832	0	0
T12	38764	832	0	0
T13	298056	5481	0	0
T14	1599958	14982	0	0
T15	88704	0	0	0
T17	0	6784	0	0
T18	0	6533	0	0
T21	0	10097	0	0
T26	72	0	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T37	0	7792	0	0
T39	74808	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	8208	0	0	0
T48	120710	0	0	0
T49	0	2064	0	0
T50	0	135	0	0
T51	0	1026	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	3719755	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	196295	3014	0	0
T7	1275	0	0	0
T8	496496	34527	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	39824	832	0	0
T12	38764	832	0	0
T13	298056	5481	0	0
T14	1599958	14982	0	0
T15	88704	0	0	0
T17	0	6784	0	0
T18	0	6533	0	0
T21	0	10097	0	0
T26	72	0	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T37	0	7792	0	0
T39	74808	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	8208	0	0	0
T48	120710	0	0	0
T49	0	2064	0	0
T50	0	135	0	0
T51	0	1026	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	568114088	0	0
T1	131454	131388	0	0
T2	779618	643650	0	0
T3	25689	23387	0	0
T4	324695	185567	0	0
T5	89118	69170	0	0
T6	278336	193010	0	0
T7	1275	1176	0	0
T8	496496	576005	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0
T11	39824	19912	0	0
T12	38764	19382	0	0
T13	298056	147378	0	0
T14	799979	792152	0	0
T15	0	44352	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	568114088	0	0
T1	131454	131388	0	0
T2	779618	643650	0	0
T3	25689	23387	0	0
T4	324695	185567	0	0
T5	89118	69170	0	0
T6	278336	193010	0	0
T7	1275	1176	0	0
T8	496496	576005	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0
T11	39824	19912	0	0
T12	38764	19382	0	0
T13	298056	147378	0	0
T14	799979	792152	0	0
T15	0	44352	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	3719755	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	196295	3014	0	0
T7	1275	0	0	0
T8	496496	34527	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	39824	832	0	0
T12	38764	832	0	0
T13	298056	5481	0	0
T14	1599958	14982	0	0
T15	88704	0	0	0
T17	0	6784	0	0
T18	0	6533	0	0
T21	0	10097	0	0
T26	72	0	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T37	0	7792	0	0
T39	74808	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	8208	0	0	0
T48	120710	0	0	0
T49	0	2064	0	0
T50	0	135	0	0
T51	0	1026	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	3719755	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	196295	3014	0	0
T7	1275	0	0	0
T8	496496	34527	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	39824	832	0	0
T12	38764	832	0	0
T13	298056	5481	0	0
T14	1599958	14982	0	0
T15	88704	0	0	0
T17	0	6784	0	0
T18	0	6533	0	0
T21	0	10097	0	0
T26	72	0	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T37	0	7792	0	0
T39	74808	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	8208	0	0	0
T48	120710	0	0	0
T49	0	2064	0	0
T50	0	135	0	0
T51	0	1026	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	3719755	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	196295	3014	0	0
T7	1275	0	0	0
T8	496496	34527	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	39824	832	0	0
T12	38764	832	0	0
T13	298056	5481	0	0
T14	1599958	14982	0	0
T15	88704	0	0	0
T17	0	6784	0	0
T18	0	6533	0	0
T21	0	10097	0	0
T26	72	0	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T37	0	7792	0	0
T39	74808	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	8208	0	0	0
T48	120710	0	0	0
T49	0	2064	0	0
T50	0	135	0	0
T51	0	1026	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	3719755	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	196295	3014	0	0
T7	1275	0	0	0
T8	496496	34527	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	39824	832	0	0
T12	38764	832	0	0
T13	298056	5481	0	0
T14	1599958	14982	0	0
T15	88704	0	0	0
T17	0	6784	0	0
T18	0	6533	0	0
T21	0	10097	0	0
T26	72	0	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T37	0	7792	0	0
T39	74808	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	8208	0	0	0
T48	120710	0	0	0
T49	0	2064	0	0
T50	0	135	0	0
T51	0	1026	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	5	0	976
T23	210473	1	0	1
T46	415426	0	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	1531	0	0	1
T57	813449	0	0	1
T58	138128	0	0	1
T59	6919	0	0	1
T60	307262	0	0	1
T61	465265	0	0	1
T62	6686	0	0	1
T63	11803	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	568114088	0	0
T1	131454	131388	0	0
T2	779618	643650	0	0
T3	25689	23387	0	0
T4	324695	185567	0	0
T5	89118	69170	0	0
T6	278336	193010	0	0
T7	1275	1176	0	0
T8	496496	576005	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0
T11	39824	19912	0	0
T12	38764	19382	0	0
T13	298056	147378	0	0
T14	799979	792152	0	0
T15	0	44352	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720429523	3719755	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	196295	3014	0	0
T7	1275	0	0	0
T8	496496	34527	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	39824	832	0	0
T12	38764	832	0	0
T13	298056	5481	0	0
T14	1599958	14982	0	0
T15	88704	0	0	0
T17	0	6784	0	0
T18	0	6533	0	0
T21	0	10097	0	0
T26	72	0	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T37	0	7792	0	0
T39	74808	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	8208	0	0	0
T48	120710	0	0	0
T49	0	2064	0	0
T50	0	135	0	0
T51	0	1026	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T13
1	0	Covered	T6,T8,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Unreachable
1	1	Covered	T6,T8,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T8,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150902139	26478810	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	150902139	592163	0	0
GntImpliesValid_A	150902139	592163	0	0
GrantKnown_A	150902139	26478810	0	0
IdxKnown_A	150902139	26478810	0	0
IndexIsCorrect_A	150902139	592163	0	0
LockArbDecision_A	150902139	0	0	0
NoReadyValidNoGrant_A	150902139	0	0	0
ReadyAndValidImplyGrant_A	150902139	592163	0	0
ReqAndReadyImplyGrant_A	150902139	592163	0	0
ReqImpliesValid_A	150902139	592163	0	0
ReqStaysHighUntilGranted0_M	150902139	0	0	0
RoundRobin_A	150902139	0	0	0
ValidKnown_A	150902139	26478810	0	0
gen_data_port_assertion.DataFlow_A	150902139	592163	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	26478810	0	0
T2	129597	123280	0	0
T3	2226	0	0	0
T4	139070	0	0	0
T5	19888	0	0	0
T6	82041	79064	0	0
T8	153552	260424	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	13736	0	0
T14	799979	212824	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	592163	0	0
T6	82041	2077	0	0
T8	153552	4941	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	665	0	0
T14	799979	4322	0	0
T15	44352	0	0	0
T17	0	3751	0	0
T21	0	6392	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T39	37404	0	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T49	0	2064	0	0
T50	0	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	592163	0	0
T6	82041	2077	0	0
T8	153552	4941	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	665	0	0
T14	799979	4322	0	0
T15	44352	0	0	0
T17	0	3751	0	0
T21	0	6392	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T39	37404	0	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T49	0	2064	0	0
T50	0	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	26478810	0	0
T2	129597	123280	0	0
T3	2226	0	0	0
T4	139070	0	0	0
T5	19888	0	0	0
T6	82041	79064	0	0
T8	153552	260424	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	13736	0	0
T14	799979	212824	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	26478810	0	0
T2	129597	123280	0	0
T3	2226	0	0	0
T4	139070	0	0	0
T5	19888	0	0	0
T6	82041	79064	0	0
T8	153552	260424	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	13736	0	0
T14	799979	212824	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	592163	0	0
T6	82041	2077	0	0
T8	153552	4941	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	665	0	0
T14	799979	4322	0	0
T15	44352	0	0	0
T17	0	3751	0	0
T21	0	6392	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T39	37404	0	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T49	0	2064	0	0
T50	0	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	592163	0	0
T6	82041	2077	0	0
T8	153552	4941	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	665	0	0
T14	799979	4322	0	0
T15	44352	0	0	0
T17	0	3751	0	0
T21	0	6392	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T39	37404	0	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T49	0	2064	0	0
T50	0	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	592163	0	0
T6	82041	2077	0	0
T8	153552	4941	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	665	0	0
T14	799979	4322	0	0
T15	44352	0	0	0
T17	0	3751	0	0
T21	0	6392	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T39	37404	0	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T49	0	2064	0	0
T50	0	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	592163	0	0
T6	82041	2077	0	0
T8	153552	4941	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	665	0	0
T14	799979	4322	0	0
T15	44352	0	0	0
T17	0	3751	0	0
T21	0	6392	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T39	37404	0	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T49	0	2064	0	0
T50	0	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	26478810	0	0
T2	129597	123280	0	0
T3	2226	0	0	0
T4	139070	0	0	0
T5	19888	0	0	0
T6	82041	79064	0	0
T8	153552	260424	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	13736	0	0
T14	799979	212824	0	0
T17	0	94232	0	0
T26	0	72	0	0
T27	0	94216	0	0
T28	0	117600	0	0
T29	0	648	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	592163	0	0
T6	82041	2077	0	0
T8	153552	4941	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	665	0	0
T14	799979	4322	0	0
T15	44352	0	0	0
T17	0	3751	0	0
T21	0	6392	0	0
T28	0	4615	0	0
T30	0	3570	0	0
T39	37404	0	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T49	0	2064	0	0
T50	0	135	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T8,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T13,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150902139	123099102	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	150902139	871444	0	0
GntImpliesValid_A	150902139	871444	0	0
GrantKnown_A	150902139	123099102	0	0
IdxKnown_A	150902139	123099102	0	0
IndexIsCorrect_A	150902139	871444	0	0
LockArbDecision_A	150902139	0	0	0
NoReadyValidNoGrant_A	150902139	0	0	0
ReadyAndValidImplyGrant_A	150902139	871444	0	0
ReqAndReadyImplyGrant_A	150902139	871444	0	0
ReqImpliesValid_A	150902139	871444	0	0
ReqStaysHighUntilGranted0_M	150902139	0	0	0
RoundRobin_A	150902139	0	0	0
ValidKnown_A	150902139	123099102	0	0
gen_data_port_assertion.DataFlow_A	150902139	871444	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	123099102	0	0
T1	21365	21365	0	0
T2	129597	0	0	0
T3	2226	2226	0	0
T4	139070	139070	0	0
T5	19888	19888	0	0
T6	82041	0	0	0
T8	153552	126215	0	0
T11	19912	19912	0	0
T12	19382	19382	0	0
T13	149028	133642	0	0
T14	0	579328	0	0
T15	0	44352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	871444	0	0
T8	153552	8188	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	1034	0	0
T14	799979	310	0	0
T15	44352	0	0	0
T17	0	3033	0	0
T18	0	6533	0	0
T21	0	3705	0	0
T26	72	0	0	0
T37	0	7792	0	0
T39	37404	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	1026	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	871444	0	0
T8	153552	8188	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	1034	0	0
T14	799979	310	0	0
T15	44352	0	0	0
T17	0	3033	0	0
T18	0	6533	0	0
T21	0	3705	0	0
T26	72	0	0	0
T37	0	7792	0	0
T39	37404	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	1026	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	123099102	0	0
T1	21365	21365	0	0
T2	129597	0	0	0
T3	2226	2226	0	0
T4	139070	139070	0	0
T5	19888	19888	0	0
T6	82041	0	0	0
T8	153552	126215	0	0
T11	19912	19912	0	0
T12	19382	19382	0	0
T13	149028	133642	0	0
T14	0	579328	0	0
T15	0	44352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	123099102	0	0
T1	21365	21365	0	0
T2	129597	0	0	0
T3	2226	2226	0	0
T4	139070	139070	0	0
T5	19888	19888	0	0
T6	82041	0	0	0
T8	153552	126215	0	0
T11	19912	19912	0	0
T12	19382	19382	0	0
T13	149028	133642	0	0
T14	0	579328	0	0
T15	0	44352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	871444	0	0
T8	153552	8188	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	1034	0	0
T14	799979	310	0	0
T15	44352	0	0	0
T17	0	3033	0	0
T18	0	6533	0	0
T21	0	3705	0	0
T26	72	0	0	0
T37	0	7792	0	0
T39	37404	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	1026	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	871444	0	0
T8	153552	8188	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	1034	0	0
T14	799979	310	0	0
T15	44352	0	0	0
T17	0	3033	0	0
T18	0	6533	0	0
T21	0	3705	0	0
T26	72	0	0	0
T37	0	7792	0	0
T39	37404	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	1026	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	871444	0	0
T8	153552	8188	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	1034	0	0
T14	799979	310	0	0
T15	44352	0	0	0
T17	0	3033	0	0
T18	0	6533	0	0
T21	0	3705	0	0
T26	72	0	0	0
T37	0	7792	0	0
T39	37404	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	1026	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	871444	0	0
T8	153552	8188	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	1034	0	0
T14	799979	310	0	0
T15	44352	0	0	0
T17	0	3033	0	0
T18	0	6533	0	0
T21	0	3705	0	0
T26	72	0	0	0
T37	0	7792	0	0
T39	37404	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	1026	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	123099102	0	0
T1	21365	21365	0	0
T2	129597	0	0	0
T3	2226	2226	0	0
T4	139070	139070	0	0
T5	19888	19888	0	0
T6	82041	0	0	0
T8	153552	126215	0	0
T11	19912	19912	0	0
T12	19382	19382	0	0
T13	149028	133642	0	0
T14	0	579328	0	0
T15	0	44352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150902139	871444	0	0
T8	153552	8188	0	0
T11	19912	0	0	0
T12	19382	0	0	0
T13	149028	1034	0	0
T14	799979	310	0	0
T15	44352	0	0	0
T17	0	3033	0	0
T18	0	6533	0	0
T21	0	3705	0	0
T26	72	0	0	0
T37	0	7792	0	0
T39	37404	0	0	0
T42	0	9498	0	0
T43	0	2959	0	0
T47	4104	0	0	0
T48	60355	0	0	0
T51	0	1026	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T13
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418625245	418536176	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	418625245	2256148	0	0
GntImpliesValid_A	418625245	2256148	0	0
GrantKnown_A	418625245	418536176	0	0
IdxKnown_A	418625245	418536176	0	0
IndexIsCorrect_A	418625245	2256148	0	0
LockArbDecision_A	418625245	0	0	0
NoReadyValidNoGrant_A	418625245	0	0	0
ReadyAndValidImplyGrant_A	418625245	2256148	0	0
ReqAndReadyImplyGrant_A	418625245	2256148	0	0
ReqImpliesValid_A	418625245	2256148	0	0
ReqStaysHighUntilGranted0_M	418625245	0	0	0
RoundRobin_A	418625245	5	0	976
ValidKnown_A	418625245	418536176	0	0
gen_data_port_assertion.DataFlow_A	418625245	2256148	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	418536176	0	0
T1	110089	110023	0	0
T2	520424	520370	0	0
T3	21237	21161	0	0
T4	46555	46497	0	0
T5	49342	49282	0	0
T6	114254	113946	0	0
T7	1275	1176	0	0
T8	189392	189366	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2256148	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	114254	937	0	0
T7	1275	0	0	0
T8	189392	21398	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3782	0	0
T14	0	10350	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2256148	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	114254	937	0	0
T7	1275	0	0	0
T8	189392	21398	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3782	0	0
T14	0	10350	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	418536176	0	0
T1	110089	110023	0	0
T2	520424	520370	0	0
T3	21237	21161	0	0
T4	46555	46497	0	0
T5	49342	49282	0	0
T6	114254	113946	0	0
T7	1275	1176	0	0
T8	189392	189366	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	418536176	0	0
T1	110089	110023	0	0
T2	520424	520370	0	0
T3	21237	21161	0	0
T4	46555	46497	0	0
T5	49342	49282	0	0
T6	114254	113946	0	0
T7	1275	1176	0	0
T8	189392	189366	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2256148	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	114254	937	0	0
T7	1275	0	0	0
T8	189392	21398	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3782	0	0
T14	0	10350	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2256148	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	114254	937	0	0
T7	1275	0	0	0
T8	189392	21398	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3782	0	0
T14	0	10350	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2256148	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	114254	937	0	0
T7	1275	0	0	0
T8	189392	21398	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3782	0	0
T14	0	10350	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2256148	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	114254	937	0	0
T7	1275	0	0	0
T8	189392	21398	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3782	0	0
T14	0	10350	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	5	0	976
T23	210473	1	0	1
T46	415426	0	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	1531	0	0	1
T57	813449	0	0	1
T58	138128	0	0	1
T59	6919	0	0	1
T60	307262	0	0	1
T61	465265	0	0	1
T62	6686	0	0	1
T63	11803	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	418536176	0	0
T1	110089	110023	0	0
T2	520424	520370	0	0
T3	21237	21161	0	0
T4	46555	46497	0	0
T5	49342	49282	0	0
T6	114254	113946	0	0
T7	1275	1176	0	0
T8	189392	189366	0	0
T9	1365	1270	0	0
T10	1395	1308	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418625245	2256148	0	0
T1	110089	832	0	0
T2	520424	0	0	0
T3	21237	832	0	0
T4	46555	832	0	0
T5	49342	832	0	0
T6	114254	937	0	0
T7	1275	0	0	0
T8	189392	21398	0	0
T9	1365	0	0	0
T10	1395	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3782	0	0
T14	0	10350	0	0