Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3113059	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3922153

1

T1

873

T2

4964

T3

118

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3753328	1			T1	2		T2	8281		T3	743
values[0x0]	1641213	1			T1	451		T2	425		T3	52
values[0x1]	1640671	1			T1	425		T2	454		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2212470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4822742

1

T1

874

T2

5829

T3

348

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24616	1			T1	6		T4	20		T5	79
valid_sources[0x01]	26152	1			T1	2		T4	15		T5	103
valid_sources[0x02]	24024	1			T1	5		T4	9		T5	84
valid_sources[0x03]	26039	1			T1	4		T4	16		T5	105
valid_sources[0x04]	25330	1			T1	6		T4	18		T5	86
valid_sources[0x05]	26749	1			T1	2		T4	8		T5	80
valid_sources[0x06]	28995	1			T1	2		T4	4		T5	85
valid_sources[0x07]	25092	1			T1	3		T4	11		T5	110
valid_sources[0x08]	26338	1			T1	3		T4	5		T5	104
valid_sources[0x09]	30861	1			T1	4		T4	11		T5	86
valid_sources[0x0a]	29757	1			T1	4		T4	9		T5	95
valid_sources[0x0b]	25304	1			T1	1		T4	14		T5	91
valid_sources[0x0c]	26829	1			T1	4		T4	21		T5	82
valid_sources[0x0d]	24709	1			T1	2		T4	15		T5	74
valid_sources[0x0e]	27157	1			T1	2		T4	5		T5	92
valid_sources[0x0f]	27476	1			T1	2		T4	15		T5	83
valid_sources[0x10]	28738	1			T1	6		T4	8		T5	99
valid_sources[0x11]	29819	1			T1	2		T4	15		T5	75
valid_sources[0x12]	27923	1			T1	1		T4	18		T5	108
valid_sources[0x13]	28599	1			T1	2		T4	10		T5	103
valid_sources[0x14]	28407	1			T1	2		T4	10		T5	80
valid_sources[0x15]	25771	1			T1	1		T4	23		T5	94
valid_sources[0x16]	26499	1			T4	9		T5	108		T6	36
valid_sources[0x17]	25000	1			T1	8		T4	9		T5	101
valid_sources[0x18]	23722	1			T4	10		T5	90		T6	18
valid_sources[0x19]	26339	1			T1	3		T4	10		T5	97
valid_sources[0x1a]	24946	1			T1	2		T4	9		T5	88
valid_sources[0x1b]	27271	1			T1	3		T4	10		T5	105
valid_sources[0x1c]	28125	1			T1	4		T2	452		T4	18
valid_sources[0x1d]	26263	1			T1	3		T4	12		T5	89
valid_sources[0x1e]	24824	1			T1	2		T4	15		T5	100
valid_sources[0x1f]	30913	1			T4	12		T5	83		T6	29
valid_sources[0x20]	25364	1			T1	9		T4	5		T5	117
valid_sources[0x21]	25319	1			T1	4		T4	10		T5	75
valid_sources[0x22]	28576	1			T1	5		T4	9		T5	107
valid_sources[0x23]	26963	1			T1	7		T4	14		T5	81
valid_sources[0x24]	26142	1			T1	1		T4	15		T5	98
valid_sources[0x25]	26447	1			T1	1		T4	7		T5	111
valid_sources[0x26]	23594	1			T1	2		T4	4		T5	87
valid_sources[0x27]	29521	1			T1	1		T4	16		T5	95
valid_sources[0x28]	24319	1			T1	3		T4	17		T5	74
valid_sources[0x29]	24241	1			T1	3		T4	6		T5	88
valid_sources[0x2a]	24695	1			T1	5		T4	22		T5	120
valid_sources[0x2b]	23644	1			T1	1		T4	11		T5	114
valid_sources[0x2c]	30875	1			T1	3		T4	6		T5	132
valid_sources[0x2d]	25708	1			T1	3		T4	16		T5	108
valid_sources[0x2e]	50187	1			T1	4		T2	912		T4	8
valid_sources[0x2f]	27549	1			T1	14		T4	21		T5	95
valid_sources[0x30]	27090	1			T1	4		T4	16		T5	111
valid_sources[0x31]	27704	1			T1	1		T4	19		T5	114
valid_sources[0x32]	27658	1			T1	3		T4	10		T5	99
valid_sources[0x33]	26256	1			T1	1		T4	17		T5	93
valid_sources[0x34]	25712	1			T1	3		T2	797		T4	12
valid_sources[0x35]	24397	1			T1	3		T4	11		T5	91
valid_sources[0x36]	81697	1			T1	1		T4	15		T5	84
valid_sources[0x37]	25715	1			T1	4		T4	13		T5	90
valid_sources[0x38]	28124	1			T1	9		T4	23		T5	85
valid_sources[0x39]	26090	1			T1	6		T4	12		T5	104
valid_sources[0x3a]	26138	1			T1	3		T4	8		T5	85
valid_sources[0x3b]	25434	1			T1	5		T4	16		T5	96
valid_sources[0x3c]	24186	1			T1	1		T4	11		T5	83
valid_sources[0x3d]	25847	1			T1	6		T4	8		T5	85
valid_sources[0x3e]	23896	1			T1	5		T4	6		T5	85
valid_sources[0x3f]	26181	1			T1	2		T4	13		T5	85
valid_sources[0x40]	25329	1			T1	5		T4	5		T5	90
valid_sources[0x41]	27596	1			T1	4		T4	10		T5	111
valid_sources[0x42]	24644	1			T1	3		T4	21		T5	86
valid_sources[0x43]	29781	1			T1	3		T4	24		T5	109
valid_sources[0x44]	31605	1			T1	4		T4	10		T5	109
valid_sources[0x45]	26245	1			T1	8		T4	15		T5	115
valid_sources[0x46]	26432	1			T1	3		T4	18		T5	73
valid_sources[0x47]	28199	1			T1	3		T4	10		T5	96
valid_sources[0x48]	29039	1			T1	4		T4	22		T5	133
valid_sources[0x49]	28230	1			T1	1		T4	18		T5	95
valid_sources[0x4a]	48673	1			T1	7		T4	14		T5	87
valid_sources[0x4b]	37471	1			T1	2		T4	12		T5	87
valid_sources[0x4c]	24881	1			T1	3		T4	12		T5	118
valid_sources[0x4d]	26261	1			T1	6		T4	15		T5	112
valid_sources[0x4e]	26623	1			T1	1		T2	3		T4	15
valid_sources[0x4f]	29160	1			T1	3		T4	11		T5	87
valid_sources[0x50]	25742	1			T1	1		T4	11		T5	97
valid_sources[0x51]	24554	1			T1	5		T4	8		T5	77
valid_sources[0x52]	26812	1			T1	5		T4	12		T5	126
valid_sources[0x53]	25078	1			T1	6		T4	14		T5	104
valid_sources[0x54]	26785	1			T1	2		T4	12		T5	114
valid_sources[0x55]	28732	1			T1	4		T4	7		T5	112
valid_sources[0x56]	25556	1			T1	8		T4	12		T5	96
valid_sources[0x57]	26769	1			T1	2		T4	5		T5	84
valid_sources[0x58]	26064	1			T1	3		T4	6		T5	114
valid_sources[0x59]	27024	1			T1	3		T4	7		T5	97
valid_sources[0x5a]	28029	1			T1	2		T4	2		T5	70
valid_sources[0x5b]	24861	1			T4	21		T5	98		T6	10
valid_sources[0x5c]	27807	1			T1	2		T4	11		T5	87
valid_sources[0x5d]	26642	1			T1	3		T4	6		T5	75
valid_sources[0x5e]	25190	1			T4	6		T5	96		T6	27
valid_sources[0x5f]	25086	1			T1	2		T4	9		T5	92
valid_sources[0x60]	25845	1			T1	2		T4	7		T5	105
valid_sources[0x61]	28380	1			T1	1		T4	7		T5	96
valid_sources[0x62]	26343	1			T1	2		T4	13		T5	114
valid_sources[0x63]	27972	1			T1	2		T4	13		T5	78
valid_sources[0x64]	24745	1			T1	2		T4	23		T5	95
valid_sources[0x65]	25184	1			T1	3		T4	18		T5	102
valid_sources[0x66]	27919	1			T1	1		T4	18		T5	95
valid_sources[0x67]	42738	1			T1	10		T4	9		T5	84
valid_sources[0x68]	28496	1			T1	4		T4	16		T5	83
valid_sources[0x69]	26976	1			T1	4		T4	20		T5	96
valid_sources[0x6a]	25562	1			T1	7		T4	19		T5	101
valid_sources[0x6b]	26528	1			T1	2		T4	11		T5	103
valid_sources[0x6c]	26207	1			T1	2		T4	12		T5	96
valid_sources[0x6d]	24942	1			T1	3		T4	15		T5	75
valid_sources[0x6e]	26235	1			T1	5		T4	7		T5	88
valid_sources[0x6f]	28856	1			T1	3		T4	26		T5	83
valid_sources[0x70]	31616	1			T1	3		T4	18		T5	111
valid_sources[0x71]	25253	1			T1	2		T4	18		T5	108
valid_sources[0x72]	26287	1			T1	5		T4	10		T5	86
valid_sources[0x73]	26694	1			T1	1		T4	6		T5	131
valid_sources[0x74]	24960	1			T1	4		T4	7		T5	91
valid_sources[0x75]	25827	1			T1	2		T4	11		T5	81
valid_sources[0x76]	24225	1			T1	2		T4	4		T5	101
valid_sources[0x77]	24322	1			T1	2		T4	7		T5	103
valid_sources[0x78]	25488	1			T1	1		T4	19		T5	100
valid_sources[0x79]	26876	1			T1	2		T4	10		T5	98
valid_sources[0x7a]	29836	1			T1	7		T4	13		T5	89
valid_sources[0x7b]	24813	1			T1	5		T4	17		T5	99
valid_sources[0x7c]	24914	1			T1	3		T4	21		T5	95
valid_sources[0x7d]	28466	1			T1	10		T4	7		T5	104
valid_sources[0x7e]	25675	1			T1	1		T4	10		T5	86
valid_sources[0x7f]	28602	1			T1	6		T4	15		T5	114
valid_sources[0x80]	29737	1			T1	4		T4	17		T5	110

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

940554

1

T1

1

T2

4090

T3

76

values[0x0]

all_enables

biggest_size

1503465

1

T1

448

T2

425

T3

26

values[0x1]

all_enables

biggest_size

1478134

1

T1

424

T2

449

T3

16