Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3128419

1

T1

5

T2

4196

T3

728

full_word

3920941

1

T1

873

T2

4964

T3

118

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7049010	1			T1	878		T2	9160		T3	846
auto[TlIntgErrCmd]	120	1			T110	2		T114	5		T113	9
auto[TlIntgErrData]	119	1			T110	3		T114	1		T113	13
auto[TlIntgErrBoth]	111	1			T110	5		T114	4		T113	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3754121

1

T1

2

T2

8281

T3

743

auto[1]

3295239

1

T1

876

T2

879

T3

103

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2813378	1			T1	1		T2	4191		T3	667
auto[TlIntgErrNone]	partial	auto[1]	314717	1			T1	4		T2	5		T3	61
auto[TlIntgErrNone]	full_word	auto[0]	940598	1			T1	1		T2	4090		T3	76
auto[TlIntgErrNone]	full_word	auto[1]	2980317	1			T1	872		T2	874		T3	42
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T114	3		T113	5		T129	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T110	2		T114	2		T113	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T186	1		T187	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	13	1			T113	1		T129	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T114	1		T113	5		T129	5
auto[TlIntgErrData]	partial	auto[1]	65	1			T110	2		T113	8		T129	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T188	1		T189	1		T190	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T110	1		T129	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T110	2		T113	3		T129	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T110	3		T114	4		T113	3
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T113	2		T129	1		T191	2