Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380228285	2786816	0	0
DepthKnown_A	380228285	380098749	0	0
RvalidKnown_A	380228285	380098749	0	0
WreadyKnown_A	380228285	380098749	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	2786816	0	0
T1	3210	1663	0	0
T2	153831	1663	0	0
T3	2812	0	0	0
T4	380610	4163	0	0
T5	693575	14992	0	0
T6	23445	0	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	1663	0	0
T13	0	832	0	0
T15	0	4989	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380228285	3153045	0	0
DepthKnown_A	380228285	380098749	0	0
RvalidKnown_A	380228285	380098749	0	0
WreadyKnown_A	380228285	380098749	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	3153045	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	0	0	0
T4	380610	5637	0	0
T5	693575	35255	0	0
T6	23445	0	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	2580	0	0
T15	0	2496	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380228285	188262	0	0
DepthKnown_A	380228285	380098749	0	0
RvalidKnown_A	380228285	380098749	0	0
WreadyKnown_A	380228285	380098749	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	188262	0	0
T3	2812	65	0	0
T4	380610	0	0	0
T5	693575	992	0	0
T6	23445	52	0	0
T7	83175	0	0	0
T8	68224	0	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	55094	0	0	0
T12	1963	0	0	0
T15	0	569	0	0
T17	0	806	0	0
T29	0	1362	0	0
T30	0	1189	0	0
T33	0	1035	0	0
T48	0	75	0	0
T49	0	404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380228285	452065	0	0
DepthKnown_A	380228285	380098749	0	0
RvalidKnown_A	380228285	380098749	0	0
WreadyKnown_A	380228285	380098749	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	452065	0	0
T3	2812	65	0	0
T4	380610	0	0	0
T5	693575	4778	0	0
T6	23445	52	0	0
T7	83175	0	0	0
T8	68224	0	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	55094	0	0	0
T12	1963	0	0	0
T15	0	569	0	0
T17	0	803	0	0
T29	0	6199	0	0
T30	0	1189	0	0
T33	0	4729	0	0
T48	0	351	0	0
T49	0	1785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380228285	5402474	0	0
DepthKnown_A	380228285	380098749	0	0
RvalidKnown_A	380228285	380098749	0	0
WreadyKnown_A	380228285	380098749	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	5402474	0	0
T1	3210	46	0	0
T2	153831	8328	0	0
T3	2812	781	0	0
T4	380610	740	0	0
T5	693575	14170	0	0
T6	23445	6215	0	0
T7	83175	2824	0	0
T8	68224	2450	0	0
T9	1106	9	0	0
T10	1062	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380228285	11765200	0	0
DepthKnown_A	380228285	380098749	0	0
RvalidKnown_A	380228285	380098749	0	0
WreadyKnown_A	380228285	380098749	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	11765200	0	0
T1	3210	46	0	0
T2	153831	8328	0	0
T3	2812	781	0	0
T4	380610	3139	0	0
T5	693575	55806	0	0
T6	23445	6215	0	0
T7	83175	2824	0	0
T8	68224	2450	0	0
T9	1106	9	0	0
T10	1062	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380228285	380098749	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0