Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T15
1	0	Covered	T4,T5,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T4,T5,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	673327649	524287593	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	673327649	3654588	0	0
GntImpliesValid_A	673327649	3654588	0	0
GrantKnown_A	673327649	524287593	0	0
IdxKnown_A	673327649	524287593	0	0
IndexIsCorrect_A	673327649	3654588	0	0
LockArbDecision_A	673327649	0	0	0
NoReadyValidNoGrant_A	673327649	0	0	0
ReadyAndValidImplyGrant_A	673327649	3654588	0	0
ReqAndReadyImplyGrant_A	673327649	3654588	0	0
ReqImpliesValid_A	673327649	3654588	0	0
ReqStaysHighUntilGranted0_M	673327649	0	0	0
RoundRobin_A	673327649	5	0	975
ValidKnown_A	673327649	524287593	0	0
gen_data_port_assertion.DataFlow_A	673327649	3654588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	524287593	0	0
T1	3210	3137	0	0
T2	175411	175317	0	0
T3	9676	6161	0	0
T4	561008	470298	0	0
T5	949307	1963532	0	0
T6	30901	27110	0	0
T7	158503	120768	0	0
T8	98362	83230	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0
T11	103520	51760	0	0
T12	144	72	0	0
T13	24704	12352	0	0
T15	322373	319077	0	0
T16	0	76200	0	0
T17	0	494769	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	3654588	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	6244	362	0	0
T4	561008	2515	0	0
T5	949307	18615	0	0
T6	30901	360	0	0
T7	158503	832	0	0
T8	98362	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	103520	832	0	0
T12	144	0	0	0
T13	24704	832	0	0
T15	644746	3112	0	0
T16	76200	0	0	0
T17	0	4717	0	0
T29	0	7527	0	0
T30	0	6048	0	0
T33	0	8146	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	6320	0	0
T66	0	804	0	0
T67	0	5766	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	3654588	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	6244	362	0	0
T4	561008	2515	0	0
T5	949307	18615	0	0
T6	30901	360	0	0
T7	158503	832	0	0
T8	98362	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	103520	832	0	0
T12	144	0	0	0
T13	24704	832	0	0
T15	644746	3112	0	0
T16	76200	0	0	0
T17	0	4717	0	0
T29	0	7527	0	0
T30	0	6048	0	0
T33	0	8146	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	6320	0	0
T66	0	804	0	0
T67	0	5766	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	524287593	0	0
T1	3210	3137	0	0
T2	175411	175317	0	0
T3	9676	6161	0	0
T4	561008	470298	0	0
T5	949307	1963532	0	0
T6	30901	27110	0	0
T7	158503	120768	0	0
T8	98362	83230	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0
T11	103520	51760	0	0
T12	144	72	0	0
T13	24704	12352	0	0
T15	322373	319077	0	0
T16	0	76200	0	0
T17	0	494769	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	524287593	0	0
T1	3210	3137	0	0
T2	175411	175317	0	0
T3	9676	6161	0	0
T4	561008	470298	0	0
T5	949307	1963532	0	0
T6	30901	27110	0	0
T7	158503	120768	0	0
T8	98362	83230	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0
T11	103520	51760	0	0
T12	144	72	0	0
T13	24704	12352	0	0
T15	322373	319077	0	0
T16	0	76200	0	0
T17	0	494769	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	3654588	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	6244	362	0	0
T4	561008	2515	0	0
T5	949307	18615	0	0
T6	30901	360	0	0
T7	158503	832	0	0
T8	98362	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	103520	832	0	0
T12	144	0	0	0
T13	24704	832	0	0
T15	644746	3112	0	0
T16	76200	0	0	0
T17	0	4717	0	0
T29	0	7527	0	0
T30	0	6048	0	0
T33	0	8146	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	6320	0	0
T66	0	804	0	0
T67	0	5766	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	3654588	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	6244	362	0	0
T4	561008	2515	0	0
T5	949307	18615	0	0
T6	30901	360	0	0
T7	158503	832	0	0
T8	98362	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	103520	832	0	0
T12	144	0	0	0
T13	24704	832	0	0
T15	644746	3112	0	0
T16	76200	0	0	0
T17	0	4717	0	0
T29	0	7527	0	0
T30	0	6048	0	0
T33	0	8146	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	6320	0	0
T66	0	804	0	0
T67	0	5766	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	3654588	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	6244	362	0	0
T4	561008	2515	0	0
T5	949307	18615	0	0
T6	30901	360	0	0
T7	158503	832	0	0
T8	98362	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	103520	832	0	0
T12	144	0	0	0
T13	24704	832	0	0
T15	644746	3112	0	0
T16	76200	0	0	0
T17	0	4717	0	0
T29	0	7527	0	0
T30	0	6048	0	0
T33	0	8146	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	6320	0	0
T66	0	804	0	0
T67	0	5766	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	3654588	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	6244	362	0	0
T4	561008	2515	0	0
T5	949307	18615	0	0
T6	30901	360	0	0
T7	158503	832	0	0
T8	98362	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	103520	832	0	0
T12	144	0	0	0
T13	24704	832	0	0
T15	644746	3112	0	0
T16	76200	0	0	0
T17	0	4717	0	0
T29	0	7527	0	0
T30	0	6048	0	0
T33	0	8146	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	6320	0	0
T66	0	804	0	0
T67	0	5766	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	5	0	975
T30	118307	1	0	1
T31	48723	0	0	1
T32	33060	0	0	1
T48	112949	0	0	1
T49	260498	0	0	1
T52	42456	0	0	1
T53	208325	0	0	1
T59	10079	0	0	1
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	1007	0	0	1
T73	120847	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	524287593	0	0
T1	3210	3137	0	0
T2	175411	175317	0	0
T3	9676	6161	0	0
T4	561008	470298	0	0
T5	949307	1963532	0	0
T6	30901	27110	0	0
T7	158503	120768	0	0
T8	98362	83230	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0
T11	103520	51760	0	0
T12	144	72	0	0
T13	24704	12352	0	0
T15	322373	319077	0	0
T16	0	76200	0	0
T17	0	494769	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673327649	3654588	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	6244	362	0	0
T4	561008	2515	0	0
T5	949307	18615	0	0
T6	30901	360	0	0
T7	158503	832	0	0
T8	98362	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	103520	832	0	0
T12	144	0	0	0
T13	24704	832	0	0
T15	644746	3112	0	0
T16	76200	0	0	0
T17	0	4717	0	0
T29	0	7527	0	0
T30	0	6048	0	0
T33	0	8146	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	6320	0	0
T66	0	804	0	0
T67	0	5766	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147567081	29247355	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	147567081	652637	0	0
GntImpliesValid_A	147567081	652637	0	0
GrantKnown_A	147567081	29247355	0	0
IdxKnown_A	147567081	29247355	0	0
IndexIsCorrect_A	147567081	652637	0	0
LockArbDecision_A	147567081	0	0	0
NoReadyValidNoGrant_A	147567081	0	0	0
ReadyAndValidImplyGrant_A	147567081	652637	0	0
ReqAndReadyImplyGrant_A	147567081	652637	0	0
ReqImpliesValid_A	147567081	652637	0	0
ReqStaysHighUntilGranted0_M	147567081	0	0	0
RoundRobin_A	147567081	0	0	0
ValidKnown_A	147567081	29247355	0	0
gen_data_port_assertion.DataFlow_A	147567081	652637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	29247355	0	0
T3	3432	3432	0	0
T4	90199	0	0	0
T5	127866	277464	0	0
T6	3728	3728	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	72	0	0
T13	12352	0	0	0
T15	322373	218720	0	0
T17	0	95264	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	652637	0	0
T3	3432	275	0	0
T4	90199	0	0	0
T5	127866	4229	0	0
T6	3728	258	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	3108	0	0
T17	0	2173	0	0
T29	0	7527	0	0
T30	0	4621	0	0
T33	0	3033	0	0
T65	0	4041	0	0
T66	0	804	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	652637	0	0
T3	3432	275	0	0
T4	90199	0	0	0
T5	127866	4229	0	0
T6	3728	258	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	3108	0	0
T17	0	2173	0	0
T29	0	7527	0	0
T30	0	4621	0	0
T33	0	3033	0	0
T65	0	4041	0	0
T66	0	804	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	29247355	0	0
T3	3432	3432	0	0
T4	90199	0	0	0
T5	127866	277464	0	0
T6	3728	3728	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	72	0	0
T13	12352	0	0	0
T15	322373	218720	0	0
T17	0	95264	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	29247355	0	0
T3	3432	3432	0	0
T4	90199	0	0	0
T5	127866	277464	0	0
T6	3728	3728	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	72	0	0
T13	12352	0	0	0
T15	322373	218720	0	0
T17	0	95264	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	652637	0	0
T3	3432	275	0	0
T4	90199	0	0	0
T5	127866	4229	0	0
T6	3728	258	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	3108	0	0
T17	0	2173	0	0
T29	0	7527	0	0
T30	0	4621	0	0
T33	0	3033	0	0
T65	0	4041	0	0
T66	0	804	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	652637	0	0
T3	3432	275	0	0
T4	90199	0	0	0
T5	127866	4229	0	0
T6	3728	258	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	3108	0	0
T17	0	2173	0	0
T29	0	7527	0	0
T30	0	4621	0	0
T33	0	3033	0	0
T65	0	4041	0	0
T66	0	804	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	652637	0	0
T3	3432	275	0	0
T4	90199	0	0	0
T5	127866	4229	0	0
T6	3728	258	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	3108	0	0
T17	0	2173	0	0
T29	0	7527	0	0
T30	0	4621	0	0
T33	0	3033	0	0
T65	0	4041	0	0
T66	0	804	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	652637	0	0
T3	3432	275	0	0
T4	90199	0	0	0
T5	127866	4229	0	0
T6	3728	258	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	3108	0	0
T17	0	2173	0	0
T29	0	7527	0	0
T30	0	4621	0	0
T33	0	3033	0	0
T65	0	4041	0	0
T66	0	804	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	29247355	0	0
T3	3432	3432	0	0
T4	90199	0	0	0
T5	127866	277464	0	0
T6	3728	3728	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	72	0	0
T13	12352	0	0	0
T15	322373	218720	0	0
T17	0	95264	0	0
T29	0	200768	0	0
T30	0	128732	0	0
T31	0	22136	0	0
T32	0	28112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	652637	0	0
T3	3432	275	0	0
T4	90199	0	0	0
T5	127866	4229	0	0
T6	3728	258	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	3108	0	0
T17	0	2173	0	0
T29	0	7527	0	0
T30	0	4621	0	0
T33	0	3033	0	0
T65	0	4041	0	0
T66	0	804	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T15
1	0	Covered	T4,T5,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T4,T5,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T15
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147567081	116936420	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	147567081	781894	0	0
GntImpliesValid_A	147567081	781894	0	0
GrantKnown_A	147567081	116936420	0	0
IdxKnown_A	147567081	116936420	0	0
IndexIsCorrect_A	147567081	781894	0	0
LockArbDecision_A	147567081	0	0	0
NoReadyValidNoGrant_A	147567081	0	0	0
ReadyAndValidImplyGrant_A	147567081	781894	0	0
ReqAndReadyImplyGrant_A	147567081	781894	0	0
ReqImpliesValid_A	147567081	781894	0	0
ReqStaysHighUntilGranted0_M	147567081	0	0	0
RoundRobin_A	147567081	0	0	0
ValidKnown_A	147567081	116936420	0	0
gen_data_port_assertion.DataFlow_A	147567081	781894	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	116936420	0	0
T2	21580	21580	0	0
T3	3432	0	0	0
T4	90199	89738	0	0
T5	127866	992589	0	0
T6	3728	0	0	0
T7	37664	37664	0	0
T8	15069	15069	0	0
T11	51760	51760	0	0
T12	72	0	0	0
T13	12352	12352	0	0
T15	0	100357	0	0
T16	0	76200	0	0
T17	0	399505	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	781894	0	0
T4	90199	10	0	0
T5	127866	1297	0	0
T6	3728	0	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	4	0	0
T16	76200	0	0	0
T17	0	2544	0	0
T30	0	1427	0	0
T33	0	5113	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	2279	0	0
T67	0	5766	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	781894	0	0
T4	90199	10	0	0
T5	127866	1297	0	0
T6	3728	0	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	4	0	0
T16	76200	0	0	0
T17	0	2544	0	0
T30	0	1427	0	0
T33	0	5113	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	2279	0	0
T67	0	5766	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	116936420	0	0
T2	21580	21580	0	0
T3	3432	0	0	0
T4	90199	89738	0	0
T5	127866	992589	0	0
T6	3728	0	0	0
T7	37664	37664	0	0
T8	15069	15069	0	0
T11	51760	51760	0	0
T12	72	0	0	0
T13	12352	12352	0	0
T15	0	100357	0	0
T16	0	76200	0	0
T17	0	399505	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	116936420	0	0
T2	21580	21580	0	0
T3	3432	0	0	0
T4	90199	89738	0	0
T5	127866	992589	0	0
T6	3728	0	0	0
T7	37664	37664	0	0
T8	15069	15069	0	0
T11	51760	51760	0	0
T12	72	0	0	0
T13	12352	12352	0	0
T15	0	100357	0	0
T16	0	76200	0	0
T17	0	399505	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	781894	0	0
T4	90199	10	0	0
T5	127866	1297	0	0
T6	3728	0	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	4	0	0
T16	76200	0	0	0
T17	0	2544	0	0
T30	0	1427	0	0
T33	0	5113	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	2279	0	0
T67	0	5766	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	781894	0	0
T4	90199	10	0	0
T5	127866	1297	0	0
T6	3728	0	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	4	0	0
T16	76200	0	0	0
T17	0	2544	0	0
T30	0	1427	0	0
T33	0	5113	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	2279	0	0
T67	0	5766	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	781894	0	0
T4	90199	10	0	0
T5	127866	1297	0	0
T6	3728	0	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	4	0	0
T16	76200	0	0	0
T17	0	2544	0	0
T30	0	1427	0	0
T33	0	5113	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	2279	0	0
T67	0	5766	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	781894	0	0
T4	90199	10	0	0
T5	127866	1297	0	0
T6	3728	0	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	4	0	0
T16	76200	0	0	0
T17	0	2544	0	0
T30	0	1427	0	0
T33	0	5113	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	2279	0	0
T67	0	5766	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	116936420	0	0
T2	21580	21580	0	0
T3	3432	0	0	0
T4	90199	89738	0	0
T5	127866	992589	0	0
T6	3728	0	0	0
T7	37664	37664	0	0
T8	15069	15069	0	0
T11	51760	51760	0	0
T12	72	0	0	0
T13	12352	12352	0	0
T15	0	100357	0	0
T16	0	76200	0	0
T17	0	399505	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147567081	781894	0	0
T4	90199	10	0	0
T5	127866	1297	0	0
T6	3728	0	0	0
T7	37664	0	0	0
T8	15069	0	0	0
T11	51760	0	0	0
T12	72	0	0	0
T13	12352	0	0	0
T15	322373	4	0	0
T16	76200	0	0	0
T17	0	2544	0	0
T30	0	1427	0	0
T33	0	5113	0	0
T48	0	311	0	0
T49	0	3937	0	0
T65	0	2279	0	0
T67	0	5766	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378193487	378103818	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	378193487	2220057	0	0
GntImpliesValid_A	378193487	2220057	0	0
GrantKnown_A	378193487	378103818	0	0
IdxKnown_A	378193487	378103818	0	0
IndexIsCorrect_A	378193487	2220057	0	0
LockArbDecision_A	378193487	0	0	0
NoReadyValidNoGrant_A	378193487	0	0	0
ReadyAndValidImplyGrant_A	378193487	2220057	0	0
ReqAndReadyImplyGrant_A	378193487	2220057	0	0
ReqImpliesValid_A	378193487	2220057	0	0
ReqStaysHighUntilGranted0_M	378193487	0	0	0
RoundRobin_A	378193487	5	0	975
ValidKnown_A	378193487	378103818	0	0
gen_data_port_assertion.DataFlow_A	378193487	2220057	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	378103818	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	2220057	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	87	0	0
T4	380610	2505	0	0
T5	693575	13089	0	0
T6	23445	102	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	2220057	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	87	0	0
T4	380610	2505	0	0
T5	693575	13089	0	0
T6	23445	102	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	378103818	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	378103818	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	2220057	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	87	0	0
T4	380610	2505	0	0
T5	693575	13089	0	0
T6	23445	102	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	2220057	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	87	0	0
T4	380610	2505	0	0
T5	693575	13089	0	0
T6	23445	102	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	2220057	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	87	0	0
T4	380610	2505	0	0
T5	693575	13089	0	0
T6	23445	102	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	2220057	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	87	0	0
T4	380610	2505	0	0
T5	693575	13089	0	0
T6	23445	102	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	5	0	975
T30	118307	1	0	1
T31	48723	0	0	1
T32	33060	0	0	1
T48	112949	0	0	1
T49	260498	0	0	1
T52	42456	0	0	1
T53	208325	0	0	1
T59	10079	0	0	1
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	1007	0	0	1
T73	120847	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	378103818	0	0
T1	3210	3137	0	0
T2	153831	153737	0	0
T3	2812	2729	0	0
T4	380610	380560	0	0
T5	693575	693479	0	0
T6	23445	23382	0	0
T7	83175	83104	0	0
T8	68224	68161	0	0
T9	1106	1020	0	0
T10	1062	1002	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378193487	2220057	0	0
T1	3210	832	0	0
T2	153831	832	0	0
T3	2812	87	0	0
T4	380610	2505	0	0
T5	693575	13089	0	0
T6	23445	102	0	0
T7	83175	832	0	0
T8	68224	832	0	0
T9	1106	0	0	0
T10	1062	0	0	0
T11	0	832	0	0
T13	0	832	0	0