Module Definition
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Module : spi_cmdparse
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.84 100.00 93.26 100.00 95.92 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_cmdparse 97.84 100.00 93.26 100.00 95.92 100.00



Module Instance : tb.dut.u_cmdparse

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.84 100.00 93.26 100.00 95.92 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.84 100.00 93.26 100.00 95.92 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_cmdparse
Line No.TotalCoveredPercent
TOTAL108108100.00
CONT_ASSIGN8511100.00
ALWAYS9033100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
ALWAYS18544100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20411100.00
ALWAYS20844100.00
ALWAYS21866100.00
ALWAYS23377100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25411100.00
ALWAYS26355100.00
CONT_ASSIGN27911100.00
ALWAYS2831111100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30411100.00
ALWAYS30744100.00
ALWAYS3154848100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
90 1 1
91 1 1
92 1 1
156 1 1
160 1 1
185 1 1
186 1 1
187 1 1
189 1 1
MISSING_ELSE
194 1 1
196 1 1
198 1 1
200 1 1
202 1 1
204 1 1
208 1 1
209 1 1
210 1 1
211 1 1
MISSING_ELSE
218 1 1
219 1 1
225 1 1
226 1 1
227 1 1
228 1 1
MISSING_ELSE
233 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
MISSING_ELSE
MISSING_ELSE
253 1 1
254 1 1
263 1 1
269 1 1
271 1 1
272 1 1
273 1 1
MISSING_ELSE
279 1 1
283 1 1
284 1 1
285 1 1
286 1 1
287 1 1
288 2 2
MISSING_ELSE
289 2 2
MISSING_ELSE
290 2 2
MISSING_ELSE
MISSING_ELSE
295 1 1
302 1 1
303 1 1
304 1 1
307 1 1
308 1 1
309 1 1
310 1 1
==> MISSING_ELSE
315 1 1
317 1 1
318 1 1
320 1 1
321 1 1
323 1 1
325 1 1
327 1 1
329 1 1
330 1 1
332 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
340 1 1
345 1 1
346 1 1
347 1 1
348 1 1
349 1 1
351 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
364 1 1
372 1 1
376 1 1
377 1 1
381 1 1
384 1 1
388 1 1
391 1 1
401 1 1
403 1 1
404 1 1
MISSING_ELSE
409 1 1
411 1 1
413 1 1
415 1 1
417 1 1
419 1 1
421 1 1
424 1 1
426 1 1


Cond Coverage for Module : spi_cmdparse
TotalCoveredPercent
Conditions898393.26
Logical898393.26
Non-Logical00
Event00

 LINE       187
 EXPRESSION (cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode))
             ---------------------1--------------------    ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T4
11CoveredT2,T4,T5

 LINE       187
 SUB-EXPRESSION (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)
                ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       194
 EXPRESSION (cmd_info_i[CmdInfoReadJedecId].valid && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode))
             ------------------1-----------------    ------------------------2------------------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T4,T5
11CoveredT4,T5,T8

 LINE       194
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadJedecId].opcode)
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       196
 EXPRESSION (cmd_info_i[CmdInfoReadSfdp].valid && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode))
             ----------------1----------------    -----------------------2----------------------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT2,T4,T5
11CoveredT2,T4,T5

 LINE       196
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadSfdp].opcode)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       198
 EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoEn4B].valid && (data_i == cmd_info_i[CmdInfoEn4B].opcode))
             -----------1----------    --------------2--------------    ---------------------3--------------------
-1--2--3-StatusTests
011CoveredT5,T17,T30
101CoveredT2,T3,T5
110CoveredT4,T5,T15
111CoveredT4,T5,T15

 LINE       198
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEn4B].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       200
 EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoEx4B].valid && (data_i == cmd_info_i[CmdInfoEx4B].opcode))
             -----------1----------    --------------2--------------    ---------------------3--------------------
-1--2--3-StatusTests
011CoveredT5,T17,T30
101CoveredT2,T3,T5
110CoveredT4,T5,T13
111CoveredT4,T5,T13

 LINE       200
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEx4B].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       202
 EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoWrEn].valid && (data_i == cmd_info_i[CmdInfoWrEn].opcode))
             -----------1----------    --------------2--------------    ---------------------3--------------------
-1--2--3-StatusTests
011CoveredT4,T5,T17
101CoveredT2,T3,T5
110CoveredT4,T5,T15
111CoveredT4,T5,T15

 LINE       202
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrEn].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       204
 EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoWrDi].valid && (data_i == cmd_info_i[CmdInfoWrDi].opcode))
             -----------1----------    --------------2--------------    ---------------------3--------------------
-1--2--3-StatusTests
011CoveredT4,T5,T15
101CoveredT2,T3,T5
110CoveredT4,T5,T13
111CoveredT4,T5,T13

 LINE       204
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrDi].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       210
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T4,T5
11CoveredT4,T5,T7

 LINE       210
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       240
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----
-1--2--3-StatusTests
011CoveredT2,T4,T5
101Not Covered
110CoveredT1,T2,T3
111CoveredT2,T4,T5

 LINE       240
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------
-1--2-StatusTests
01CoveredT2,T7,T11
10CoveredT2,T4,T5
11CoveredT2,T4,T5

 LINE       242
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       271
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----
-1--2--3-StatusTests
011CoveredT2,T4,T5
101Not Covered
110CoveredT1,T2,T3
111CoveredT2,T4,T5

 LINE       271
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       279
 EXPRESSION (cmd_info_d.upload && ((!sck_status_busy_i)))
             --------1--------    -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT49,T107,T86
11CoveredT4,T5,T15

 LINE       295
 EXPRESSION ((cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle) || (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle))
             -----------------------------1----------------------------    -----------------------------2----------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T7,T15
10CoveredT5,T7,T8

 LINE       295
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle)
                -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T8

 LINE       295
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle)
                -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T15

 LINE       302
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T7

 LINE       304
 EXPRESSION (in_flashmode || in_passthrough)
             ------1-----    -------2------
-1--2-StatusTests
00Not Covered
01CoveredT1,T5,T7
10CoveredT1,T2,T3

 LINE       327
 EXPRESSION (module_active && data_valid_i && cmd_info_d.valid)
             ------1------    ------2-----    --------3-------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT2,T4,T5
111CoveredT2,T4,T5

 LINE       384
 EXPRESSION (opcode_en4b ? DpEn4B : DpEx4B)
             -----1-----
-1-StatusTests
0CoveredT4,T5,T13
1CoveredT4,T5,T15

 LINE       391
 EXPRESSION (opcode_wren ? DpWrEn : DpWrDi)
             -----1-----
-1-StatusTests
0CoveredT4,T5,T15
1CoveredT4,T5,T15

 LINE       401
 EXPRESSION (module_active && data_valid_i)
             ------1------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T5

FSM Coverage for Module : spi_cmdparse
Summary for FSM :: st
TotalCoveredPercent
States 9 9 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAddr4B 381 Covered T4,T5,T13
StIdle 240 Covered T1,T2,T3
StJedec 346 Covered T4,T5,T15
StReadCmd 372 Covered T4,T5,T7
StSfdp 358 Covered T4,T5,T15
StStatus 335 Covered T4,T5,T7
StUpload 376 Covered T4,T5,T15
StWait 340 Covered T2,T4,T5
StWrEn 388 Covered T4,T5,T15


transitionsLine No.CoveredTests
StIdle->StAddr4B 381 Covered T4,T5,T13
StIdle->StJedec 346 Covered T4,T5,T15
StIdle->StReadCmd 372 Covered T4,T5,T7
StIdle->StSfdp 358 Covered T4,T5,T15
StIdle->StStatus 335 Covered T4,T5,T7
StIdle->StUpload 376 Covered T4,T5,T15
StIdle->StWait 340 Covered T2,T4,T5
StIdle->StWrEn 388 Covered T4,T5,T15



Branch Coverage for Module : spi_cmdparse
Line No.TotalCoveredPercent
Branches 49 47 95.92
IF 187 2 2 100.00
IF 210 2 2 100.00
IF 218 3 3 100.00
IF 240 2 2 100.00
IF 271 2 2 100.00
IF 283 8 8 100.00
IF 307 3 2 66.67
CASE 325 27 26 96.30

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 187 if ((cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)))

Branches:
-1-StatusTests
1 Covered T2,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 210 if ((cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)))

Branches:
-1-StatusTests
1 Covered T4,T5,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 218 if ((!rst_ni)) -2-: 226 if (latch_cmdinfo)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T4,T5
0 0 Covered T2,T4,T5


LineNo. Expression -1-: 240 if ((((st == StIdle) && module_active) && data_valid_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 271 if ((((st == StIdle) && module_active) && data_valid_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if ((!rst_ni)) -2-: 287 if (intercept_d) -3-: 288 if (opcode_readstatus) -4-: 289 if (opcode_readjedec) -5-: 290 if (opcode_readsfdp)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 1 - - Covered T5,T7,T40
0 1 0 - - Covered T5,T39,T58
0 1 - 1 - Covered T5,T39,T50
0 1 - 0 - Covered T5,T7,T40
0 1 - - 1 Covered T5,T58,T50
0 1 - - 0 Covered T5,T7,T39
0 0 - - - Covered T2,T4,T5


LineNo. Expression -1-: 307 if ((!rst_ni)) -2-: 309 if (module_active)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T4,T5
0 0 Not Covered


LineNo. Expression -1-: 325 case (st) -2-: 327 if (((module_active && data_valid_i) && cmd_info_d.valid)) -3-: 332 case (1'b1) -4-: 334 if (in_flashmode) -5-: 336 if (cfg_intercept_en_status_i) -6-: 345 if (in_flashmode) -7-: 347 if (cfg_intercept_en_jedec_i) -8-: 357 if (in_flashmode) -9-: 359 if (cfg_intercept_en_sfdp_i) -10-: 384 (opcode_en4b) ? -11-: 391 (opcode_wren) ? -12-: 401 if ((module_active && data_valid_i))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12-StatusTests
StIdle 1 opcode_readstatus 1 - - - - - - - - Covered T4,T15,T17
StIdle 1 opcode_readstatus 0 1 - - - - - - - Covered T5,T7,T40
StIdle 1 opcode_readstatus 0 0 - - - - - - - Covered T11,T16,T28
StIdle 1 opcode_readjedec - - 1 - - - - - - Covered T4,T15,T17
StIdle 1 opcode_readjedec - - 0 1 - - - - - Covered T5,T39,T50
StIdle 1 opcode_readjedec - - 0 0 - - - - - Covered T5,T11,T58
StIdle 1 opcode_readsfdp - - - - 1 - - - - Covered T4,T15,T17
StIdle 1 opcode_readsfdp - - - - 0 1 - - - Covered T5,T58,T50
StIdle 1 opcode_readsfdp - - - - 0 0 - - - Covered T5,T16,T50
StIdle 1 opcode_readcmd - - - - - - - - - Covered T4,T5,T7
StIdle 1 upload - - - - - - - - - Covered T4,T5,T15
StIdle 1 opcode_en4b opcode_ex4b - - - - - - 1 - - Covered T4,T5,T15
StIdle 1 opcode_en4b opcode_ex4b - - - - - - 0 - - Covered T4,T5,T13
StIdle 1 opcode_wren opcode_wrdi - - - - - - - 1 - Covered T4,T5,T15
StIdle 1 opcode_wren opcode_wrdi - - - - - - - 0 - Covered T4,T5,T15
StIdle 1 default - - - - - - - - - Covered T2,T4,T5
StIdle 0 - - - - - - - - - 1 Covered T1,T2,T3
StIdle 0 - - - - - - - - - 0 Covered T1,T2,T3
StStatus - - - - - - - - - - - Covered T4,T5,T7
StJedec - - - - - - - - - - - Covered T4,T5,T15
StSfdp - - - - - - - - - - - Covered T4,T5,T15
StReadCmd - - - - - - - - - - - Covered T4,T5,T7
StUpload - - - - - - - - - - - Covered T4,T5,T15
StAddr4B - - - - - - - - - - - Covered T4,T5,T13
StWrEn - - - - - - - - - - - Covered T4,T5,T15
StWait - - - - - - - - - - - Covered T2,T4,T5
default - - - - - - - - - - - Not Covered


Assert Coverage for Module : spi_cmdparse
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CmdOnlySelDpKnown_A 147567081 116936420 0 0
OnlyOneDatapath_A 147567081 59448 0 0
SelDpKnown_A 147567081 116936420 0 0
StKnown_A 147567081 116936420 0 0


CmdOnlySelDpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 147567081 116936420 0 0
T2 21580 21580 0 0
T3 3432 0 0 0
T4 90199 89738 0 0
T5 127866 992589 0 0
T6 3728 0 0 0
T7 37664 37664 0 0
T8 15069 15069 0 0
T11 51760 51760 0 0
T12 72 0 0 0
T13 12352 12352 0 0
T15 0 100357 0 0
T16 0 76200 0 0
T17 0 399505 0 0

OnlyOneDatapath_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 147567081 59448 0 0
T2 21580 3 0 0
T3 3432 0 0 0
T4 90199 90 0 0
T5 127866 370 0 0
T6 3728 0 0 0
T7 37664 18 0 0
T8 15069 8 0 0
T11 51760 10 0 0
T12 72 0 0 0
T13 12352 8 0 0
T15 0 82 0 0
T16 0 16 0 0
T17 0 247 0 0

SelDpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 147567081 116936420 0 0
T2 21580 21580 0 0
T3 3432 0 0 0
T4 90199 89738 0 0
T5 127866 992589 0 0
T6 3728 0 0 0
T7 37664 37664 0 0
T8 15069 15069 0 0
T11 51760 51760 0 0
T12 72 0 0 0
T13 12352 12352 0 0
T15 0 100357 0 0
T16 0 76200 0 0
T17 0 399505 0 0

StKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 147567081 116936420 0 0
T2 21580 21580 0 0
T3 3432 0 0 0
T4 90199 89738 0 0
T5 127866 992589 0 0
T6 3728 0 0 0
T7 37664 37664 0 0
T8 15069 15069 0 0
T11 51760 51760 0 0
T12 72 0 0 0
T13 12352 12352 0 0
T15 0 100357 0 0
T16 0 76200 0 0
T17 0 399505 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%