Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3731622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4483027

1

T1

5

T2

988

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4486220	1			T1	1		T2	206		T3	2
values[0x0]	1864116	1			T1	8		T2	447		T3	4
values[0x1]	1864313	1			T1	8		T2	449		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2648017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5566632

1

T1

7

T2

1007

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28306	1			T2	2		T4	199		T5	63
valid_sources[0x01]	32227	1			T2	3		T4	203		T5	46
valid_sources[0x02]	29723	1			T2	5		T4	125		T5	53
valid_sources[0x03]	32413	1			T2	7		T4	174		T5	48
valid_sources[0x04]	31980	1			T2	1		T4	172		T5	56
valid_sources[0x05]	33269	1			T2	9		T4	205		T5	77
valid_sources[0x06]	30517	1			T2	3		T4	244		T5	32
valid_sources[0x07]	31448	1			T2	2		T4	244		T5	51
valid_sources[0x08]	30069	1			T2	3		T4	172		T5	51
valid_sources[0x09]	32020	1			T2	4		T4	218		T5	67
valid_sources[0x0a]	30038	1			T2	3		T4	190		T5	48
valid_sources[0x0b]	32896	1			T2	4		T4	214		T5	52
valid_sources[0x0c]	33873	1			T2	2		T4	193		T5	68
valid_sources[0x0d]	30090	1			T2	5		T4	274		T5	47
valid_sources[0x0e]	31184	1			T2	1		T4	174		T5	69
valid_sources[0x0f]	29679	1			T2	3		T4	167		T5	59
valid_sources[0x10]	29772	1			T2	5		T4	163		T5	58
valid_sources[0x11]	31396	1			T2	9		T4	193		T5	59
valid_sources[0x12]	35407	1			T2	4		T4	256		T5	54
valid_sources[0x13]	30655	1			T2	10		T4	240		T5	47
valid_sources[0x14]	31588	1			T2	8		T4	158		T5	42
valid_sources[0x15]	31138	1			T2	2		T4	207		T5	60
valid_sources[0x16]	31264	1			T2	5		T4	209		T5	46
valid_sources[0x17]	31478	1			T2	3		T4	184		T5	43
valid_sources[0x18]	33680	1			T2	3		T4	206		T5	50
valid_sources[0x19]	30326	1			T2	6		T4	157		T5	60
valid_sources[0x1a]	30806	1			T2	9		T4	282		T5	56
valid_sources[0x1b]	31385	1			T2	3		T4	218		T5	66
valid_sources[0x1c]	30806	1			T2	7		T4	195		T5	62
valid_sources[0x1d]	28598	1			T2	3		T4	128		T5	48
valid_sources[0x1e]	31632	1			T2	7		T4	133		T5	61
valid_sources[0x1f]	33485	1			T2	6		T4	191		T5	51
valid_sources[0x20]	27785	1			T4	187		T5	66		T7	2
valid_sources[0x21]	31321	1			T2	6		T4	150		T5	47
valid_sources[0x22]	30700	1			T2	3		T4	247		T5	77
valid_sources[0x23]	31004	1			T2	6		T4	182		T5	51
valid_sources[0x24]	37187	1			T2	4		T4	254		T5	48
valid_sources[0x25]	31689	1			T2	8		T4	229		T5	53
valid_sources[0x26]	31934	1			T2	8		T4	247		T5	31
valid_sources[0x27]	31064	1			T2	7		T4	212		T5	42
valid_sources[0x28]	31725	1			T2	1		T4	237		T5	26
valid_sources[0x29]	30744	1			T2	3		T4	254		T5	49
valid_sources[0x2a]	32504	1			T2	8		T4	167		T5	58
valid_sources[0x2b]	31918	1			T2	4		T4	325		T5	39
valid_sources[0x2c]	28215	1			T2	6		T4	286		T5	52
valid_sources[0x2d]	29357	1			T2	7		T4	191		T5	52
valid_sources[0x2e]	30897	1			T2	3		T4	143		T5	53
valid_sources[0x2f]	29914	1			T2	7		T4	145		T5	57
valid_sources[0x30]	31917	1			T2	1		T4	184		T5	52
valid_sources[0x31]	31143	1			T2	8		T4	184		T5	39
valid_sources[0x32]	36576	1			T2	2		T4	238		T5	57
valid_sources[0x33]	29757	1			T2	8		T4	209		T5	50
valid_sources[0x34]	56529	1			T2	7		T4	221		T5	58
valid_sources[0x35]	30662	1			T2	5		T4	204		T5	50
valid_sources[0x36]	31656	1			T2	9		T4	232		T5	49
valid_sources[0x37]	30297	1			T2	8		T4	193		T5	39
valid_sources[0x38]	30949	1			T2	7		T4	154		T5	35
valid_sources[0x39]	30308	1			T2	1		T4	216		T5	35
valid_sources[0x3a]	32797	1			T2	5		T4	168		T5	43
valid_sources[0x3b]	31182	1			T2	4		T4	130		T5	71
valid_sources[0x3c]	30146	1			T2	6		T4	205		T5	49
valid_sources[0x3d]	29312	1			T2	11		T4	172		T5	45
valid_sources[0x3e]	30311	1			T2	1		T4	189		T5	32
valid_sources[0x3f]	32246	1			T2	3		T4	160		T5	56
valid_sources[0x40]	31045	1			T2	6		T4	168		T5	46
valid_sources[0x41]	32898	1			T2	6		T4	213		T5	31
valid_sources[0x42]	28457	1			T2	7		T4	160		T5	42
valid_sources[0x43]	29890	1			T2	4		T4	203		T5	37
valid_sources[0x44]	33538	1			T2	6		T4	125		T5	44
valid_sources[0x45]	31022	1			T2	5		T4	149		T5	51
valid_sources[0x46]	30956	1			T2	1		T4	163		T5	36
valid_sources[0x47]	28935	1			T2	7		T4	119		T5	40
valid_sources[0x48]	30762	1			T2	6		T4	269		T5	67
valid_sources[0x49]	35509	1			T2	4		T4	204		T5	47
valid_sources[0x4a]	29501	1			T2	4		T4	195		T5	60
valid_sources[0x4b]	31406	1			T2	7		T4	232		T5	43
valid_sources[0x4c]	29344	1			T2	8		T4	144		T5	48
valid_sources[0x4d]	39687	1			T2	4		T4	230		T5	37
valid_sources[0x4e]	49618	1			T2	4		T4	172		T5	55
valid_sources[0x4f]	31285	1			T2	3		T4	167		T5	52
valid_sources[0x50]	35898	1			T2	4		T4	239		T5	38
valid_sources[0x51]	33039	1			T2	2		T4	147		T5	45
valid_sources[0x52]	30547	1			T2	5		T4	166		T5	29
valid_sources[0x53]	29818	1			T2	2		T4	286		T5	43
valid_sources[0x54]	35526	1			T2	7		T4	144		T5	49
valid_sources[0x55]	32812	1			T2	3		T4	139		T5	53
valid_sources[0x56]	28782	1			T2	13		T4	257		T5	48
valid_sources[0x57]	34141	1			T2	2		T4	224		T5	56
valid_sources[0x58]	30675	1			T2	2		T4	181		T5	61
valid_sources[0x59]	30471	1			T2	5		T4	139		T5	60
valid_sources[0x5a]	28114	1			T2	6		T4	174		T5	64
valid_sources[0x5b]	30125	1			T2	2		T4	192		T5	40
valid_sources[0x5c]	31799	1			T2	5		T4	242		T5	70
valid_sources[0x5d]	30214	1			T2	2		T4	177		T5	45
valid_sources[0x5e]	41333	1			T2	6		T4	180		T5	46
valid_sources[0x5f]	34089	1			T2	7		T4	238		T5	48
valid_sources[0x60]	31854	1			T2	2		T4	267		T5	42
valid_sources[0x61]	31370	1			T2	4		T4	247		T5	43
valid_sources[0x62]	32644	1			T2	1		T4	216		T5	54
valid_sources[0x63]	29755	1			T2	3		T4	216		T5	48
valid_sources[0x64]	32975	1			T2	7		T4	215		T5	59
valid_sources[0x65]	31513	1			T4	184		T5	45		T7	4
valid_sources[0x66]	31929	1			T2	5		T4	219		T5	29
valid_sources[0x67]	31955	1			T2	1		T4	208		T5	57
valid_sources[0x68]	31147	1			T2	3		T4	233		T5	53
valid_sources[0x69]	30372	1			T2	3		T4	84		T5	31
valid_sources[0x6a]	28910	1			T2	2		T4	201		T5	56
valid_sources[0x6b]	34198	1			T2	4		T4	185		T5	59
valid_sources[0x6c]	29465	1			T2	4		T4	165		T5	54
valid_sources[0x6d]	30900	1			T2	4		T4	175		T5	52
valid_sources[0x6e]	31202	1			T2	2		T4	198		T5	64
valid_sources[0x6f]	31505	1			T2	5		T4	205		T5	49
valid_sources[0x70]	30273	1			T2	2		T4	219		T5	41
valid_sources[0x71]	30555	1			T2	4		T4	270		T5	39
valid_sources[0x72]	29850	1			T2	6		T4	178		T5	55
valid_sources[0x73]	31775	1			T2	8		T4	228		T5	44
valid_sources[0x74]	35265	1			T2	4		T4	225		T5	56
valid_sources[0x75]	30572	1			T2	6		T4	188		T5	64
valid_sources[0x76]	31548	1			T2	3		T4	317		T5	54
valid_sources[0x77]	33411	1			T2	7		T4	198		T5	90
valid_sources[0x78]	33061	1			T2	4		T4	198		T5	48
valid_sources[0x79]	29811	1			T2	2		T4	166		T5	51
valid_sources[0x7a]	35211	1			T2	2		T4	192		T5	51
valid_sources[0x7b]	32176	1			T2	5		T4	241		T5	38
valid_sources[0x7c]	33357	1			T2	1		T4	286		T5	55
valid_sources[0x7d]	30271	1			T2	6		T4	198		T5	66
valid_sources[0x7e]	29539	1			T2	2		T4	176		T5	34
valid_sources[0x7f]	30245	1			T2	6		T4	215		T5	50
valid_sources[0x80]	30549	1			T2	7		T4	217		T5	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1102744

1

T1

1

T2

95

T4

2294

values[0x0]

all_enables

biggest_size

1703308

1

T1

3

T2

446

T3

3

values[0x1]

all_enables

biggest_size

1676975

1

T1

1

T2

447

T3

4