Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3750333

1

T1

12

T2

114

T3

4

full_word

4482002

1

T1

5

T2

988

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8231905	1			T1	17		T2	1102		T3	11
auto[TlIntgErrCmd]	139	1			T99	9		T100	9		T104	5
auto[TlIntgErrData]	159	1			T99	12		T100	6		T104	6
auto[TlIntgErrBoth]	132	1			T99	9		T100	5		T104	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4487676

1

T1

1

T2

206

T3

2

auto[1]

3744659

1

T1

16

T2

896

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3384654	1			T2	111		T3	2		T4	27567
auto[TlIntgErrNone]	partial	auto[1]	365289	1			T1	12		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1102823	1			T1	1		T2	95		T4	2294
auto[TlIntgErrNone]	full_word	auto[1]	3379139	1			T1	4		T2	893		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T99	4		T100	5		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T99	5		T100	3		T104	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T100	1		T104	1		T143	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T104	1		T116	1		T144	1
auto[TlIntgErrData]	partial	auto[0]	77	1			T99	6		T100	4		T104	3
auto[TlIntgErrData]	partial	auto[1]	69	1			T99	6		T100	1		T104	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T143	1		T163	2		T164	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T100	1		T104	1		T165	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T99	4		T100	2		T104	3
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T99	4		T100	2		T104	6
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T116	1		T163	2		T146	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T99	1		T100	1		T165	1