Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491914368	3053464	0	0
DepthKnown_A	491914368	491779601	0	0
RvalidKnown_A	491914368	491779601	0	0
WreadyKnown_A	491914368	491779601	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	3053464	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	6662	0	0
T5	375343	1664	0	0
T6	1243	0	0	0
T7	4194	832	0	0
T8	507203	16633	0	0
T9	11796	832	0	0
T10	231533	9991	0	0
T11	345343	0	0	0
T13	0	4159	0	0
T15	0	1664	0	0
T25	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491914368	3571365	0	0
DepthKnown_A	491914368	491779601	0	0
RvalidKnown_A	491914368	491779601	0	0
WreadyKnown_A	491914368	491779601	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	3571365	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	23937	0	0
T5	375343	1664	0	0
T6	1243	0	0	0
T7	4194	832	0	0
T8	507203	10816	0	0
T9	11796	3596	0	0
T10	231533	25818	0	0
T11	345343	0	0	0
T13	0	6382	0	0
T15	0	833	0	0
T25	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491914368	202364	0	0
DepthKnown_A	491914368	491779601	0	0
RvalidKnown_A	491914368	491779601	0	0
WreadyKnown_A	491914368	491779601	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	202364	0	0
T4	249624	593	0	0
T5	375343	1268	0	0
T6	1243	0	0	0
T7	4194	0	0	0
T8	507203	547	0	0
T9	11796	0	0	0
T10	231533	603	0	0
T11	345343	1058	0	0
T12	195213	596	0	0
T13	0	1025	0	0
T24	840	0	0	0
T25	0	100	0	0
T26	0	813	0	0
T28	0	438	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491914368	515225	0	0
DepthKnown_A	491914368	491779601	0	0
RvalidKnown_A	491914368	491779601	0	0
WreadyKnown_A	491914368	491779601	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	515225	0	0
T4	249624	2763	0	0
T5	375343	1268	0	0
T6	1243	0	0	0
T7	4194	0	0	0
T8	507203	547	0	0
T9	11796	0	0	0
T10	231533	2714	0	0
T11	345343	4816	0	0
T12	195213	596	0	0
T13	0	4189	0	0
T24	840	0	0	0
T25	0	100	0	0
T26	0	813	0	0
T28	0	438	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491914368	6499414	0	0
DepthKnown_A	491914368	491779601	0	0
RvalidKnown_A	491914368	491779601	0	0
WreadyKnown_A	491914368	491779601	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	6499414	0	0
T1	901	17	0	0
T2	173325	271	0	0
T3	1414	11	0	0
T4	249624	49404	0	0
T5	375343	10162	0	0
T6	1243	38	0	0
T7	4194	203	0	0
T8	507203	2058	0	0
T9	11796	72	0	0
T10	231533	3222	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491914368	15057702	0	0
DepthKnown_A	491914368	491779601	0	0
RvalidKnown_A	491914368	491779601	0	0
WreadyKnown_A	491914368	491779601	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	15057702	0	0
T1	901	17	0	0
T2	173325	270	0	0
T3	1414	11	0	0
T4	249624	196900	0	0
T5	375343	9979	0	0
T6	1243	38	0	0
T7	4194	203	0	0
T8	507203	2047	0	0
T9	11796	270	0	0
T10	231533	13024	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491914368	491779601	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0